1) is it possible to pull the EN1 signal to ground on the CPLD and switch off the SoM buck converter (FPGA 1.0V) in software? Using the board as is, with only CPLD bitstream changes.
2) is the source code for the CPLD firmware available?
Which artix 7 module did you mean?
we have several products with artix:
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Artix-7/
br
John
yes, sorry: it is the te0712 a200t
i see that the te0711 has a dedicated pwr_dis output on the CPLD. not all artix7 SoMs are alike in this matter.
But still it should be feasible to repurpose EN1 on the te0712 for this purpose, even though it is supposed to be just a CPLD input.
Hi,
please need a email to support@trenz-electronic.de
br
John