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#1
UltraScale / Re: PCIe conectivity with TEF1...
Last post by KellyRansome - June 17, 2025, 05:19:58 AMWhile focusing on custom projects can be efficient, fully understanding the reference design's flash programming process for PCIe initialization might be crucial for troubleshooting. Different boot configurations can be tricky, and bypassing the standard procedure could introduce unforeseen issues. Could some missing steps in the standard reference flow indicate bad parenting ?
#2
Trenz Electronic FPGA Modules / Re: Help Needed: Best Starter ...
Last post by KellyRansome - June 17, 2025, 05:14:33 AMWhile the default files can get you started, I've found that projects often benefit from tailored constraints for optimal performance in Vivado 2023.1. Exploring some advanced clocking wizard options could also unlock some additional functionality within the PMOD interfaces. What sort of throughput are you hoping to achieve? Perhaps not considering these factors from the start might lead to bad parenting, in a design sense, of course.
#3
UltraScale / Re: TE0808 starter kit selecti...
Last post by MA - June 16, 2025, 10:47:13 AMHi,
I apologise, but unfortunately a mistake has crept in and the board files are not up to date, as with the StarterKit design. However, you can use variant 91 (TE0808-05-9GI21-E) without any problems.
If you want to have the current board files, please download the StarterKit design and copy the complete folder "board_files" into your design. This is probably the easiest way.
br Manuela
I apologise, but unfortunately a mistake has crept in and the board files are not up to date, as with the StarterKit design. However, you can use variant 91 (TE0808-05-9GI21-E) without any problems.
If you want to have the current board files, please download the StarterKit design and copy the complete folder "board_files" into your design. This is probably the easiest way.
br Manuela
#4
UltraScale / TE0808 starter kit selection
Last post by sr_lm - June 12, 2025, 03:59:59 PMI have purchased this module: AMD-Zynq-Ultrascale-ZU9EG-2I-4-GByte-DDR4 TE0808-05-9GI81-E
When I downloaded the FPGA Reference Design and ran the _create_setup_linux.sh, it's missing the TE0808-05-9GI81-E as a module selection options (see attached screenshot). Is there an alternative that I could use from that list? Or is there a newer version of the reference design which includes this module?
When I downloaded the FPGA Reference Design and ran the _create_setup_linux.sh, it's missing the TE0808-05-9GI81-E as a module selection options (see attached screenshot). Is there an alternative that I could use from that list? Or is there a newer version of the reference design which includes this module?
#5
Trenz Electronic FPGA Modules / Re: TE0701 / TE0711 UART Pins
Last post by haraldmz - June 10, 2025, 08:45:54 AMQuote from: Antti Lukats on June 05, 2025, 10:16:45 AMHi,
all you need is to read the TE0701 TRM, it is all explained there:
https://wiki.trenz-electronic.de/display/PD/TE0701+TRM
There is a diagram that shows that the CPLD is "forwarding" the UART pins, and a bit later is defined to WHAT pins the forwarding is done. So all the information you need is there.
Ah, I missed the table further down. Thanks for the clarification.
#6
Trenz Electronic FPGA Modules / Re: Project starting point for...
Last post by tomwhite - June 09, 2025, 07:43:46 AMYes, the TE0630-reference_design-EDK-13.2-v1.0.4ca0645.zip is an official starting point for the TE0630, but it's based on the older EDK 13.2 toolchain.
#7
Trenz Electronic FPGA Modules / Re: JTAG connection error on J...
Last post by tomwhite - June 09, 2025, 07:40:00 AMYou can confirm and restore JTAG functionality on your TE0820-5 by updating the CPLD firmware using the Lattice Diamond Programmer with the correct JED file for your PCB revision. Ensure the JTAGEN pin is set low, verify DIP switch settings, and avoid applying 3.3V to Bank 66, which is 1.8V tolerant.
#8
Trenz Electronic FPGA Modules / Re: JTAG Not Working On TE0720...
Last post by tomwhite - June 09, 2025, 07:32:43 AMYou should double-check that the JTAG cable and USB drivers are properly installed and recognized by your PC, and try swapping the dip switch settings to match the TE0720 default JTAG configuration from the Trenz documentation
#9
UltraScale / Re: TE0865-02+TEBT0865+KK0865
Last post by mer - June 05, 2025, 05:47:47 PMOk, thanks for the reply. Let me ask this then, do you have a schematic/documentation for the little JTAG/UART board that is plugged into JB1 on the carrier? There are a couple switches on there that I'm not sure what they do. Thanks.
#10
UltraScale / Re: TE0865-02+TEBT0865+KK0865
Last post by Antti Lukats - June 05, 2025, 10:24:03 AMTEBT0865 is TEST basis (the second T stands for TEST) to just test TE0865 is alive. It was designed much earlier than KK0865, hence there is no PWM Fan header on this board. The design support for TEBT0865 is currently limited to Schematic that is available from downloads.