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please read also this pdf of the old design (same place like the design file download):
we have also done manually changes on the petalinx project (in step 3 you say you has generate a new one, this means really new petalinux project or did you use our template?).

sorry I can give only limited support of this old reference designs.

Hi my friends .
I have two board of Trenz electronic , TE0720 (main board) and TE0701-06 (carrier board).

I go the steps in  " " for run petalinux on TE0720 but after packaging and copy BOOT.BIN and image.ub on SD card petalinux don't run !!! :(

when I use example in one file of " " not problems.

The steps I have taken are as follows :
1- Install vivado 2017.4 and  petalinux 2017.4 and bsp ZED-board  (Only to test my installation)
2- Run in petalinux folder
3- Create new project by petalinux (zynq)
4- Create new project by vivado and export hard ware (.hdf)
5- Change path of CONFIG_TMP_DIR_LOCATION variable to your project path "<plnx-proj-root>/build/tmp" manually
6- Petalinux-config --get-hw-description
7- Run:$ petalinux-config
8- Run:$ petalinux-config -c kernel
9- Run:$ petalinux-config -c rootfs
10- Run:$ petalinux-build
11- Run:$ petalinux-package --boot --fsbl /.../zynq_fsbl.elf --fpga /.../design_1_wrapper.bit  --u-boot
12- copy BOOT.BIN and image.ub from images folder to SD card

I do not know where the problem comes from?
Please help me. thanks
Hello Deepak,
sorry, but I can't help you to debug your project.
The only thing that I can mention that you need to check SPI settings,
Frequency, CPHA, CPOL should correspond device you trying to communicate.

Best regards
Oleksandr Kiyenko
Solved by rebooting the PC  :)
Hi all,

I am unable to program the TE0802 R5 processor, as it shows this error:

xsct% Info: Cortex-R5 #0 (target 8) Stopped at 0x0 (Cannot resume. AP transaction error, DAP status 0x30000021)

I am generating a project with the default Trenz configuration, it used to work fine. Then I tried to configure the FPGA using some bitstream file using xsct (fpga <bitstream>)

Now I am back to my previous project with the SDK, without any changes in SW or FPGA. I see the PL gets written but now I cannot access the R5.

Any ideas?

xsct% targets
  1  PS TAP
     2  PMU
     3  PL
       13  Legacy Debug Hub
  4  PSU (JTAG port open error. AP transaction error, DAP status 0x30000021)
     7  RPU
        8* Cortex-R5 #0 (Cannot resume. AP transaction error, DAP status 0x30000021)
        9  Cortex-R5 #1 (Reset)
    10  APU
       11  Cortex-A53 #0 (Breakpoint, EL3(S)/A64)
       12  Cortex-A53 #1 (Power On Reset)

Trenz Electronic FPGA Modules / Re: Check SPI communication in Zynqberry
« Last post by Deepak on May 05, 2021, 05:25:08 PM »
Hello Kiyenko,

Thanks for your reply.

I made the SPI clk and SPI chip_select signals also as external pins and routed them to respective GPIO pins.

J8 Pin              Name               Zynq Pin          Signal
19                   GPIO10             H14                SPI0_MOSI_O_0
21                   GPIO9               J13                 SPI0_MISO_I_0
23                  GPIO11            J15                 SPI0_SCLK_O_0
24                  GPIO8            L15                 SPI0_SS_O_0

I assigned the signals to the respective GPIO pins based on the Brickpi3 schematics I got from these websites.

The spi loopback test ( receives the sent data when I loop the GPIO 19 and 21 pins and run the program.
But still same error when trying to communicate with Brickpi3 "No SPI Response".

Could you please tell me how I can troubleshoot this error further ?

Thanks for your time and consideration.

Best Regards
Trenz Electronic FPGA Modules / Re: Getting Started with TE0714
« Last post by JH on May 05, 2021, 08:06:17 AM »

TEBA0714-01 is a simple breakout board without power connector. You must connect laboratory power supply to one of the 3.3V Pin (for example J17-5, J17-46, J20-5, J20-46, J4-5, J3-5), see also schematics:

For Variable Bank powers, check which assembly version you has bough.

Additional documentation and links to download for the carrier and the module:

Regarding JX1 XMOD connector. I would recommend to use XMOD(this one with Xilinx License on programmer) but you can also use Xilinx programmer.
With XMOD you has also the possibility to use UART over the XMOD Programmer. Here are some more information about the XMOD:

BOOTMODE Pin can be floating for Master QSPI mode.

Yes it looks correct like you has described:
JX1-4 (TCK)is input  from the module
JX1-8 (TDO) is output from the module
JX1-10 (TDI) is is input from the module
JX1-12 (TMS) is is input from the module

V_CFG is JTAGVREF (which depends on module assembly variant)
And GND is alsoGND


Hello Deepak,
your workflow is OK. I prefer to assign pins in xdc file manually, but both ways are good.
Yes, you need to assign SPI CLK and CS pins to make SPI interface works.

Oleksandr Kiyenko
Trenz Electronic FPGA Modules / Re: Check SPI communication in Zynqberry
« Last post by Deepak on May 04, 2021, 05:38:51 PM »
Hello Kiyenko,

Thanks for your reply.

I realized the J8 pins 19 and 21 are Zynq pins H14 and J13 respectively. I mentioned it as R12 and P15 before. I am sorry, I dint read the schematics properly.

J8 Pin              Name               Zynq Pin
19                   GPIO10             H14
21                   GPIO9               J13

After I added SPI0 in Zynq PS and made MISO and MOSI as external. I selected 'Run Implementation'.

After Implementation, I unplaced Zynq Pin H14 and J13 mapped to the GPIO signals (GPIO_1_tri_io[7] and GPIO_1_tri_io[8]) and mapped the MISO and MOSI signals to those Zynq package pins and selected 'Run Implementation'. Vivado assigns the 'package pin' ( M12 and K12 ) automatically to the GPIO pins (GPIO_1_tri_io[7] and GPIO_1_tri_io[8]) which were unplaced by me before. I removed these automatic assignment made and selected 'Generate Bit stream'.

That time it issued an error saying 'GPIO 19 and GPIO 21' pins are not placed and bit stream was not generated.

But, if I leave the automatic assignment of signals (GPIO_1_tri_io[7] and GPIO_1_tri_io[8]) to package pins (M12 and K12) as it is and run 'Generate Bitstream', the bit stream was generated successfully.

I used this bitstream to build petalinux image for the Zynqberry and programmed it with the new BOOT.bin created with the new hardware file (zsys_wrapper.bit) . I looped the GPIO pins 19 and 21 using jumper wire and I ran the spi loopback test C-program and was able to receive the sent data.

Could you please tell me if the process I followed is correct in Vivado ? If we unplace any signal and if Vivado automatically assigns a package pin to it, will it be fine or will it cause any damage to the device ?

But now when I connect Zynqberry to Brickpi3, and run the example sensor program it still issues 'No SPI response ERROR'. Should I make the other SPI signals (clock and chip select) also external ?

Thanks for your time and consideration.

Hello Deepak,
from your screenshots, it's not clear what causes this error. Please find the error description in the "Messages" tab.

Oleksandr Kiyenko
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