Hello,
looking at the schematics ( SCH-TE0701-05.PDF and SCH-TE0712-01.PDF ) I noticed that FMC_CLK0_P (on TE0701) is connected to B16_L13_N (on XC7A200T). Is this correct ?
I am asking because the name of the FMC signal implies it should be connected to the P side of a clock capable pin.
Best regards,
Viorel
I will read VITA 57.1 once more, but I think it only talks about DIFFERENTIAL clocks, not at all about single ended clocks.
So compliant FMC cards should use only differential clocks, but unfortunately not all FMC card vendors comply.
Also the FMC_CLK0_N signal is connected to B16_L13_P so a differential clock ( on the FMC_CLK0 pair ) will appear inverted in the FPGA. I am just asking to make sure that this is really the case. In the schematics I can also see the connections to TE0720. In that case FMC_CLK0_P does to the P side and FMC_CLK0_N goes to the N side.
Best regards,
Viorel
Yes this is the case, confirmed.