Hi!
We are using a TE0820 module on a custom board and are trying to get a Marvell 88E1512 PHY attached to GEM0 using SGMII working.
The PHY is detected as it seems, and a link up is shown, but no network connectivity is working.
dmesg output:
[ 3.632724] macb ff0b0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0b0000 irq 37 (xx:xx:xx:xx:xx:xx)
[ 11.726497] macb ff0b0000.ethernet eth0: PHY [ff0b0000.ethernet-ffffffff:00] driver [Marvell 88E1510] (irq=POLL)
[ 11.736698] macb ff0b0000.ethernet eth0: configuring for phy/sgmii link mode
[ 15.886309] macb ff0b0000.ethernet eth0: unable to generate target frequency: 125000000 Hz
[ 15.895703] macb ff0b0000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
[ 15.938093] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
This is our device tree configuration in system-user.dtsi:
&gem0 {
phy-handle = <&phy1>;
local-mac-address = [xx xx xx xx xx xx];
xlnx,has-mdio = <1>;
gem0_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: phy1@0 {
reset-gpios = <&gpio 78 GPIO_ACTIVE_LOW>;
compatible = "marvell,88e1510";
reg = <0x0>;
marvell,reg-init = <0x12 0x14 0x0201>; // Set PHY to SGMII mode
};
};
};
Hi,
which Version of Petalinux are you on?
marvell,reg-init looks wrong, should be 4 entries.... where did you get this from?
https://github.com/Xilinx/linux-xlnx/blob/xlnx_rebase_v5.15_2022.2/drivers/net/phy/marvell.c#L472
We are using PetaLinux 2022.2, with a design based on the test_board example by Trenz.
We just fixed the issue.
The configuration of the Si5338 clock chip was probably invalid, we replaced it using the configuration taken from the 2019.2 TEF1002 example (which defines outputs 2 and 3 as 125 MHz, just as we need), and it immediately worked.
I think we took the property from some posts on the Xilinx forum, it does indeed seem misformatted.
We removed this property from the device tree, and it does seem it is not needed, the PHY works without that property in place.
Thank you for your help.
Best regards