Author Topic: TEF1002 with TE0820 as PCIE endpoint  (Read 311 times)

paule

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TEF1002 with TE0820 as PCIE endpoint
« on: October 04, 2021, 06:54:38 PM »
Hello,

I am interested in using the TEF1002/TE0820 combination (Ultrasoc+ MPSOC) as a PCIe endpoint that supports hardware acceleration using some IP I have developed. I simply need a way of passing blocks of data in each direction, between a PC/server (running Ubuntu) with a root complex and the TEF1002 end point (running petalinux on ARM), however I'm very new to PCIe.

Is there a reference design that would help me to do this? It could be using the built in PCIe controller in the PS or via the PL, whichever is the easiest route to pass data over the PCIe interface to the endpoint DRAM. Whilst I can find some useful Xilinx resource for a root complex there seems to be very little for an endpoint, other than a bare metal application that is no longer available.

Thanks!
Paul.

JH

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Re: TEF1002 with TE0820 as PCIE endpoint
« Reply #1 on: October 04, 2021, 08:00:59 PM »
Hello,
we have only this one:
https://wiki.trenz-electronic.de/display/PD/TE0820+TD+TEF1002
PCIe is configured as endpoint and you can see it as Xilinx device on the PC where the Card is connected. But it's without any drivers, so it's a start point but not more.

You should also ask on Xilinx forum. The community is bigger, so you should get a quicker answer that will help you better.
br
John

paule

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Re: TEF1002 with TE0820 as PCIE endpoint
« Reply #2 on: October 25, 2021, 12:50:48 PM »
Dear John,

Thank you for your earlier reply.

Following up on this topic, and for the benefit of others, I would like to report the following:

It seems that Xilinx do not currently support a Linux PCIe endpoint on the PS side of an Ultrascale+ MPSoC device (AR 70702), so this will not be possible until kernel support is added.

I also considered an alternative approach using a hardware design on the PL side, however the PL side uses a different set of transceivers and these do not appear to be wired up on the TE0820. It seems therefore that this would not be possible using a  TEF1002/TE0820 combination as there is simply no route to the PCIe connector from the PL side? Please correct me if this is wrong and I missed something?

Thanks,
Paul.


JH

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Re: TEF1002 with TE0820 as PCIE endpoint
« Reply #3 on: October 26, 2021, 01:49:24 PM »
Hi,
did I oversee something?
Xilinx didn't say it's not supported on AR70702: https://support.xilinx.com/s/article/70702?language=en_US


Xilinx will not provide any drivers, but it doesn't means that's not supported. It  is very often the case that you have to write drivers by yourself or hire an external company.  Especially for complicated interfaces like pcie. Sometime they provide examples, but only fore there own evalboard. often they work also on other board with similar connection or with small modification.
I'm sorry but there is rarely a simple solution.

br
John

paule

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Re: TEF1002 with TE0820 as PCIE endpoint
« Reply #4 on: October 26, 2021, 02:34:02 PM »
Hi John,

I perhaps should not have used the word "support", what I mean is that there isn't currently a Xilinx provided Linux driver for a PS-PCIe endpoint, so as you say customers will need to write their own.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/85983409/Xilinx+PCIe+Root+Port

However, I have heard from another source that Xilinx have received a number of requests for such a driver and are hoping to target 2022.1 for this.

BR,

Paul.