Could you supply UCF-files and a top.vhd (with a pre defined entity declaration) for the TE0712?
UCF files are used by legacy ISE tools that are obsoleted since 2013 by Xilinx.
All 7 series design should be done by Vivado, for vivado we do provide board awareness files.
If you need UCF the easiest way to generate them is to use pinout excel table and export them from there
I have seen (and installed) the awareness files (board_part.xml and mig.prj).
I want to try the workflow and first steps with my old (virtex4-)design, that I have to adept to a new Artix7 / Zynq7.
I checked the board_part.xml but I am not sure, why there is a naming with P0, P1, ... that is totally different to the naming conventions in the module connector schematics.
I wonder if I have to search for example P16_L16_P in the schematics and see that it ends at B20 at the FPGA and search this physical port B20 in the board_part.xml to find the name P1_i(0) and P1_o(0).
Maybe I only need the predefined complete entity declaration?
Joern