Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: razi marjani on October 20, 2013, 02:22:08 PM

Title: MCB Placement error
Post by: razi marjani on October 20, 2013, 02:22:08 PM
HI
I've used TE0600-GigaBee_XC6LX-Axi-EDK-13.2-v1.0.f79134d.zip as a start point for my project and it works fine.
Then I added My custom IP and I tried to generate bitstream.
But I encountered whit this error.

ERROR:Place - ConstraintResolved NO placeable site for
   MCB1_DDR3/MCB1_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0
ERROR:Place - ConstraintResolved NO placeable site for
   MCB3_DDR3/MCB3_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0
ERROR:Place:1172 - The BUFLL/BUFPLL_MCB instance
   <MCB1_DDR3/MCB1_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0> needs to
   have all of its IOB loads placed into its same IO bank. However, due to
   user-specified constraints, the BUFLL/BUFPLL_MCB instance
   <MCB1_DDR3/MCB1_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0> and its
   IOB load <axi_s6_ddrx_0_mcbx_dram_dqs> cannot be placed in the same IO bank.
   These constraints could be LOCATION or AREA constraints on
   <MCB1_DDR3/MCB1_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0>, or
   <axi_s6_ddrx_0_mcbx_dram_dqs>, or other components connected to them, which
   could impose an implicit constraint on them. Please check user-specified
   constraints on all of these components to ensure their combination is not
   infeasible.
ERROR:Place:1172 - The BUFLL/BUFPLL_MCB instance
   <MCB3_DDR3/MCB3_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0> needs to
   have all of its IOB loads placed into its same IO bank. However, due to
   user-specified constraints, the BUFLL/BUFPLL_MCB instance
   <MCB3_DDR3/MCB3_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0> and its
   IOB load <mcbx_dram_dqs> cannot be placed in the same IO bank. These
   constraints could be LOCATION or AREA constraints on
   <MCB3_DDR3/MCB3_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0>, or
   <mcbx_dram_dqs>, or other components connected to them, which could impose an
   implicit constraint on them. Please check user-specified constraints on all
   of these components to ensure their combination is not infeasible.
ERROR:Xflow - Program map returned error code -1073741819. Aborting flow
   execution...
make: *** [__xps/system_routed] Error 1

I attach my mhs after adding my IP
Title: Re: MCB Placement error
Post by: Oleksandr Kiyenko on October 20, 2013, 02:34:23 PM
Hello Razi,

In your project you use additional clock generator which take more clock buffers than exist in FPGA.
Please read http://www.xilinx.com/support/documentation/user_guides/ug382.pdf and plan your clocking resources correct way.

Best regards
Oleksandr Kiyenko