Hi,
So I purchased a Trenz Zynqberry TE0726-03M board and was able to get a couple of demo's working and running. Now I am new to the Zynq platform and am trying to understand what the difference between MIO and EMIO connectors are, and what they have to do with the FPGA.
In a nutshell, I create a Zynqberry project using Vivado 2019.1, with a block design containing a Zynq Processing System.
I then double-click on the Zynq block and set:
* MIO Configuration => I/O Peripherals -> ENET 0 to EMIO
* MIO Configuration => I/O Peripherals -> ENET 0 -> MDIO to EMIO
After doing this, I see a bunch of pins on my Zynq Processing Block that look like a GMII connection, only thing I don't understand what they are for!
* Can I send or receive data using them?
Also, can I map pins on the FPGA directly to the EMIO? Any tips or pointers are appreciated! (I have been scanning through Xilinx documentation but I can't find the connection)
The pins I see are:
* GMII_ETHERNET_0
* ENET0_GMII_TX_EN[0:0] out
* ENET0_GMII_TX_ER[0:0] out
* ENET0_GMII_TXD[7:0] out
* ENET0_GMII_COL in
* ENET0_GMII_CRS in
* ENET0_GMII_RX_CLK in
* ENET0_GMII_RX_DV in
* ENET0_GMII_RX_ERR in
* ENET0_GMII_TX_CLK in
* ENET0_GMII_RXD[7:0] in