Is there a straightforward/simple process for migrating a project from TE0820-02-03CG-1EA (1GB) to TE0820-03-4AE21FA (2GB)? What are the steps involved and possible gotchas?
Hi,
Option 1 (the cleanest way): Create new Vivado project with TE0820-03-4AE21FA board files and add all you IPs and ZynqMP changes.
Option 2 (Should be possible, but sometimes it goes wrong(so make a copy of you old project)):
Or change board files on your existing board to TE0820-03-4AE21FA, remove ZynqMP IP, add again ZynqMP IP and run board automation for basic inistialisation, add you ZynqMP changes and connect your PL periphery again.
Option 3 :
export your block design as TCL, open TCL file with text editor and remove DDR settings from zynqMP IP properties in the tcl file (TCL export will include all PS settings).
add "apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e -config {apply_board_preset "1" } [get_bd_cells zynq_ultra_ps_e_0]" to the the TCL file befor PS properties will be load "set_property -dict [ list \..... ] $zynq_ultra_ps_e_0
create new Vivado project with TE0820-03-4AE21FA board files and load exported tcl scripts.
brJohn
Looks good, thanks for the info!
Currently using Vivado 2018.2
Is it required to move to 2018.3 to use TE0820-03-4AE21FA board files?
2018.3 board files should be work also with 18.2.
Sometimes Xilinx changed ZynqMP IP version, than it can happens that it's not longer compatible. So in case ZynqMP IP Version is the same it should work.
We add new variants only to new reference designs (it's impossible to support all Vivado Versions.) Newest TE0820 is 19.2 and we will update to 20.2.
br
John