Recent Posts

Pages: [1] 2 3 ... 10
1
Trenz Electronic FPGA Modules / TE0703-05 BOM
« Last post by sonic on June 18, 2018, 05:47:04 PM »
Hello,

I am looking for a Bill of Material for TE0703-05. I have found the Altium project and from there I can export BOM, but I would like to check exact component used for this evaluation board. Would you please send me the BOM.

Appreciate your help! Thanks!

Best Regards
2
Trenz Electronic FPGA Modules / ZynqBerry mass programming
« Last post by NZ on June 18, 2018, 04:51:16 PM »
Hallo all! The project I am currently working on for the Zynqberry is finally ready to go into production and I have now hit a bit of a wall when it comes to mass-programming Berries. So far I have programmed it using Xilinx's SDK. Now that's a beast of a program that uses tens of gigabytes for something which should be a fairly straight forward and easy task. It also means I dare not hand this over to our production guys as the SDK requires the whole project and whatever. I basically only want to hand them a small flash program, the BOOT.BIN file and the special zynq-fsbl for flashing.

I am currently struggling with Vivado Lab, which is at least a heck of a lot smaller to install (still several hundred megs!) but I can't get it to properly recognize the QSPI chip (S25FL127SABMFV10). When I add the memory configuration part I think I should choose the s25fl128s-3.3v-qspi-x4-single, as far as I can tell it's the 3.3V version and the wiki says all four lanes are connected. But it just instantly fails the moment I click 'Program' without any decent explanation is to why. Because I am stubborn I also tried other versions but they all instantly fail.

So. Long story short: is there a decent program that allows my production guys to mass program ZynqBerries with a minimal amount of effort?

If no: does anybody know of a way to achieve this goal?
3
Trenz Electronic FPGA Modules / Re: Unstable USB connetion
« Last post by Antti Lukats on June 18, 2018, 03:15:29 PM »
USB PHY does not need the reset to be toggled after initial power up. So if it works it must work without any software controlled resets applied during operation.
4
Trenz Electronic FPGA Modules / Re: Unstable USB connetion
« Last post by jlamp on June 18, 2018, 12:58:57 PM »
Hi,

Right now I am using Yocto to generate Linux distribution not Petalinux. With Yocto zc702 works but TE0720 gets stuck.

I have check Vivado project and the only difference between two boards is this MIO configuration part. Where the USB0 Reset is defined to use MIO7 zc702 but in the TE0720 not.



I can see this usb reset pin in the schematics of the zc702



In TE0720 I see that the USB reset is done through the CPLD,



So my question is how knows the CPLD when to do the reset when I unplug the camera from the USB connector and update the lsusb command?

Thanks,
Jorge

Modified, now images should be viewed
5
Trenz Electronic FPGA Modules / Re: Unstable USB connetion
« Last post by JH on June 18, 2018, 12:00:42 PM »
Hi,

i think only that's not a reset problem, because in the most cases it's a driver problem. But it can be also a reset problem. there are also much more reasons possible, which can effect this issue.
Did you checked the sources from same Vivado/Petalinux release, as you compared ZC702 and TE0720 petalinux configuration?

To your first post question:

Code: [Select]
    /*
     * Reset pulse to USB PHY
         */
        Status = XEmacPs_PhyWrite(&Emac, 0x1A,  7, 0x0010); if(Status != XST_SUCCESS){ return XST_FAILURE; }
        Status = XEmacPs_PhyWrite(&Emac, 0x1A,  7, 0x0000); if(Status != XST_SUCCESS){ return XST_FAILURE; }

Here FSBL write to CPLD and reset USB on power up. This is user code to get access to TE0720 CPLD, so it's not on zc702.

br
John
6
Trenz Electronic FPGA Modules / Re: Unstable USB connetion
« Last post by jlamp on June 18, 2018, 10:52:51 AM »
I have also created a small program to reset the USB

Code: [Select]
#include <stdio.h>
#include <fcntl.h>  // cor open
#include <unistd.h> // for close
#include <errno.h>
#include <sys/ioctl.h>
#include <linux/usbdevice_fs.h>

void main(int argc, char **argv){

        const char *filename;
        int fd;
        filename = argv[1];

        fd = open(filename, O_WRONLY);
        ioctl(fd, USBDEVFS_RESET, 0);
        close(fd);

        return;

}

And when the USB gets stuck I execute it and I see how is reset

Code: [Select]
root@hros-trenz-som:~# ./reset /dev/bus/usb/001/002
usb 1-1: USB disconnect, device number 2
root@hros-trenz-som:~# usb 1-1: new high-speed USB device number 3 using ci_hdrc

So why is not a reset problem?

Thank you very much,

Jorge
7
Trenz Electronic FPGA Modules / Re: Unstable USB connetion
« Last post by jlamp on June 18, 2018, 10:23:31 AM »
Hi John,

Kernel config is the same in both boards and also the rootfs, I created them for the TE0720 and seeing that I had no success I put the same in zc702 SDCard so I don't think the problem is here.

Another question, why I need to add

Code: [Select]
    /*
     * Reset pulse to USB PHY
         */
        Status = XEmacPs_PhyWrite(&Emac, 0x1A,  7, 0x0010); if(Status != XST_SUCCESS){ return XST_FAILURE; }
        Status = XEmacPs_PhyWrite(&Emac, 0x1A,  7, 0x0000); if(Status != XST_SUCCESS){ return XST_FAILURE; }

code in FSBL to recognize the USB? I dont' see it in the zc702 board.

Thank you very much,

Jorge
8
Trenz Electronic FPGA Modules / Re: adding si5338 driver
« Last post by JH on June 18, 2018, 08:57:57 AM »
Hi,
can you try out our prebuillt boot.bin and image.ub at first?
RTC should work with this files, for your TE0715-04-15-1I3
  • test_board\prebuilt\boot_images\04_15_1i\u-boot\BOOT.bin
  • test_board\prebuilt\os\petalinux\default\image.ub
RTC is connected to I2C1, you must add I2C  device tree entry and add driver to kernel:For FSBL, there is a template with all sources included:
  • test_board\sw_lib\sw_apps\zynq_fsbl
Changed and add files:You can include this as template into SDK (this can be used like default FSBL application), how you add local repository to SDK is described here:brJohn


9
Trenz Electronic FPGA Modules / Re: adding si5338 driver
« Last post by rawl_dog on June 16, 2018, 02:03:13 AM »
So, the RTC driver is not loaded into PetaLinux, but rather configured in the FSBL using the I2C driver?

Now my question is: How do I configure the FSBL to do so? I've definitely missed a step...

BTW, here are my error messages from the test_board console output:
hctosys: unable to open rtc device (rtc0)
hwclock: can't open '/dev/misc/rtc': No such file or directory

Thanks to everyone for the help,

Brad
10
CYC1000 community projects / SDRAM Interface
« Last post by asc1 on June 15, 2018, 04:12:17 PM »
CYC1000 comes with an SDRAM chip, but there is no SDRAM core in the Quartus IP library. According to the NIOS ref design it should be possible to use a NIOS based controller, however the ref design is incomplete (to my taste) and checking the pinout revelas that there is no clock for the SDRAM chip coming from the FPGA.
Please clarifiy how to properly use the SDRAM, preferable also without NIOS.
I use the CYC1000 for teaching and have some designs running on it, so the rest of the board is nice (few more switches would be good, though)
Pages: [1] 2 3 ... 10