I am never able to meet timing with my design using the Gigabee base. I get the following:
Derived Constraints for TS_host_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_host_clk | 10.000ns| 10.478ns| 6.355ns| 1| 0| 2569486| 131|
| TS_mdio | 400.000ns| 254.200ns| N/A| 0| 0| 131| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
but I cannot find how to change this, or even what nets are affected.
Is there a directive somewhere where this is accessable?
Thank you in advance,
David.
Hi,
check with timing analyser, what exactly the problem is. How you do this, see for example:
- https://forums.xilinx.com/t5/Welcome-Join/Timing-report-Analysis-Xilinx-ISE-14-7-Spartan-6-FPGA/td-p/722751 (https://forums.xilinx.com/t5/Welcome-Join/Timing-report-Analysis-Xilinx-ISE-14-7-Spartan-6-FPGA/td-p/722751)
What's TS_host_clk? External or internal generated?
Depending on the exact issue, reduce speed or add register or set constrains (timing,area), or maybe it's not relevant, than add TIG or ....How to solve this depends on your design and your design goal.
br
John