Hello all,
I am planing use a TE0720 in a project in which FPGA is controlling a 8 channel 125Mhz ADC. ADC use 2 lvds lanes per channel to transfer data out to FPGA. So, there should be 16 pair lvds to fetch data from the ADC.
With 14 bit adc, the lvds bit clock will as high as 400Mhz.
I am wondering if the TE0720 trace lengths or matching is good enough to use in this situation?
Any suggestion will be appropriated. Thanks ahead.
Hello,
we have module trace length available on our download page:
- https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0720/REV03/HW_Design (https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0720/REV03/HW_Design)
Device package trace length can be create with Vivado:
- for example use our scripts: TE::util_package_length --> use a separate project, for example our reference design, because this will be modified during file generation.
Either you create length match with your carrier design. Or you use IO elements of the FPGA to compensate length mismatch.
br
John