Recent posts

#91

UltraScale / Re: TE0802 Data Rate

Last post by faly477a - October 23, 2023, 03:47:05 PM

https://shop.trenz-electronic.de/de/TE0802-02-1BEV2-A-MPSoC-Development-Board-mit-AMD-Zynq-UltraScale-ZU1EG-und-1-GB-LPDDR4


Here is the link for the product.

#92

UltraScale / TE0802 Data Rate

Last post by faly477a - October 23, 2023, 03:44:30 PM

Hello Guys, my supervisor asked me to test the date rate at communication between TE0802. Is there a specific Software or tool for this test? Or should I write a test programm by myself ?


Thank you  

#93

Open source IP / Re: Labtools fmeter

Last post by ame - October 19, 2023, 11:23:38 AM

Hello,
Yes, that is possible. The Fmeter is a simple frequency counter that simply calculates the ratio between known and unknown frequencies.
br
John

Great  . Thank you for your quick reply.

#94

Open source IP / Re: Labtools fmeter

Last post by JH - October 19, 2023, 06:45:56 AM

Hello,
Yes, that is possible. The Fmeter is a simple frequency counter that simply calculates the ratio between known and unknown frequencies.
br
John

#95

Open source IP / Labtools fmeter

Last post by ame - October 18, 2023, 06:18:21 PM

Hello,

I would like to know about the Trenz IP "Labtools fmeter" IP Licence terms.
There is no Licence terms in the source files.
Is it possible to use IP in a commercial project without violating any license terms?

Regards

#96

CYC1000 community projects / Re: Utility to flash FPGA

Last post by lauryfriese - October 18, 2023, 11:13:04 AM

This is so helpful, thanks for the idea.

#97

UltraScale / Re: TE0807 clock wizard lock f...

Last post by JH - October 11, 2023, 06:57:13 AM

Hi,
I must have overlooked your answer. Sorry.
Voltages are actually measured before delivery. It is strange that it was missing. But I'm glad you were able to solve the problem.
br
John

#98

UltraScale / Re: TE0807 clock wizard lock f...

Last post by cs_wiz - October 09, 2023, 04:50:14 AM

Hi,

Yes I am programming the Si5345 in my baremetal code and the power line is also enabled.
As I mentioned in my reply post, this was due to a hardware fault. I managed to get it working after replacing the resistors.

Cheers.

#99

Trenz Electronic FPGA Modules / Re: TE0320-00ev02IB board work...

Last post by shirleyhenderson - October 05, 2023, 11:16:54 PM

Hi,
territorial io
you could simply have the HDL code generated for other device and if it is not encrypted, adjust it to be compatible with Spartan 3. The question is whether it is worth the effort. Spartan 3 is EOL anyway, which means you should develop on newer devices.
br
John

Thanks for your useful advice

#100

Trenz Electronic FPGA Modules / Re: TEBF0808 / TE0807 SFP+ Eth...

Last post by JH - October 05, 2023, 12:03:54 PM

I took the circuit from this post to get the transceiver clock onto normal interconnect and had a look at it with the ILA core and it isn't moving. I don't think a reset issue would do that because the complex ethernet core isn't involved, it's just a couple of buffers

You mean from the other post? Yes, there were only buffers in there. But if you don't connect them properly, you won't see anything.  As far as I can see, he had set the buffers correctly on the other post and then divided CLK down and simply checked whether the counter was working.
The other customer did not comment further on the lack of resistors. We do voltage tests here before delivery, so that should actually be covered.

In the end I decided to switch to another board which has multiple RJ45 1G ethernets connected to the PL using RGMII rather than transceivers so I could make progress on the main part of my project.

Ok, I'm sorry I couldn't be of more help. Good luck with your project.

br
John