Recent posts

#21

Trenz Electronic FPGA Modules / Clock on TE0715-05-51I33-A

Last post by Michael - March 05, 2024, 11:32:49 AM

Dear,

We are working with an TE0715-05-51I33-A FPGA on the TE0705 carrier board. When running the example project, there seems to be no clock going to the PL. We measure

inputs:
fclk[0] : no clock
mgt_clk1 : clock signal (as expected)

PS outputs:
FCLK_CLK0 : no clock, constant high
FCLK_RESET0_N : low (active!)

We verified that the programming works and the measured pins are connected correctly by implementing some simple asynchronous logic.

We made no modifications to the TE0705 carrier board other than adjusting the output voltages to 3V3. According to our understanding of the documentation, this should work. We did not modify the example vivado project except adding output pins to measure the previously mentioned signals.

Does somebody have an idea what the problem could be? Is there some reset we don't see that stops the clock from being produced?

#22

Trenz Electronic FPGA Modules / Re: Si5338 TE0713

Last post by MA - March 05, 2024, 10:53:12 AM

Hello,

what exactly do you want to do? TE0712 and TE0713 are two different series and therefore cannot be compared 1:1.

For the TE0712 series we have a reference design with the Si5338A-B which you can find in the following link
 - https://wiki.trenz-electronic.de/display/PD/TE0712+Test+Board

You can then find the corresponding clock-builder reference project in
 - <project_folder>\test_board\misc\PLL\SI5338

We do not currently have a reference design for the TE0713 series that includes the Si5338.

Best regards,
Manuela

#23

Trenz Electronic FPGA Modules / Re: Si5338 TE0713

Last post by ame - March 04, 2024, 02:09:06 PM

Hello,

I'm trying to configure SI5338. I getback the TE0712 ClockBuilder project, but it looks the schematic changed. The termination resistor R49 has been add on clk3 (200MHZ) and remove on CLK (125MHz).
Should I change the format output on clock builder pro?
Could you provide your clock-builder reference project?

I'm using Vhdl project https://github.com/steffenmauch/SI5338-VHDL but I obtain 87.63MHz instead of 100MHz.

Regards

(The Schematic change from TE012 to TE013.)

#24

Trenz Electronic FPGA Modules / Si5338 TE0713

Last post by ame - March 04, 2024, 02:07:37 PM

Hello,

I'm trying to configure SI5338. I getback the TE0712 ClockBuilder project, but it looks the schematic changed. The termination resistor R49 has been add on clk3 (200MHZ) and remove on CLK (125MHz).
Should I change the format output on clock builder pro?
Could you provide your clock-builder reference project?

I'm using Vhdl project https://github.com/steffenmauch/SI5338-VHDL but I obtain 87.63MHz instead of 100MHz.

Regards

#25

MAX1000 community projects / Playing ZX Spectrum in HDMI in...

Last post by Subcritical - February 22, 2024, 05:52:24 AM

Playing great new games:
https://itch.io/s/111036/full-pat-morita-pack

Capture playing Shovel Adventure:
https://youtu.be/uP6nl9aS-cw

New 4Mbytes Sdram to Sram Wrapper:
https://github.com/AtlasFPGA/zx/blob/main/atlas.max/sdram.v

New DVI/HDMI Wrapper in verilog:
https://github.com/AtlasFPGA/zx/blob/main/atlas.max/hdmi.v

#26

Trenz Electronic FPGA Modules / ZX Spetrum in MAX1000

Last post by Subcritical - February 22, 2024, 05:46:02 AM

Playing great new games:
https://itch.io/s/111036/full-pat-morita-pack

Capture playing Shovel Adventure:
https://youtu.be/uP6nl9aS-cw

New 4Mbytes Sdram to Sram Wrapper:
https://github.com/AtlasFPGA/zx/blob/main/atlas.max/sdram.v

New DVI/HDMI Wrapper in verilog:
https://github.com/AtlasFPGA/zx/blob/main/atlas.max/hdmi.v

#27

Trenz Electronic FPGA Modules / Re: TE0712 oscillators drift

Last post by ame - February 21, 2024, 08:35:15 AM

Any news about that issue?

I just switch to a pcie root-point without ssc. The drift was from the ssc root point.

Regards

#28

Trenz Electronic FPGA Modules / Re: Flash QSPI TE0820 with 202...

Last post by JH - February 14, 2024, 09:12:18 AM

Hi,
different can be QSPI is with our without design...or like I say some other issue.
Try to change boot mode to JTAG only, if it works, than it's problem with AMD software only.

Let me know if you need help again.
br
John

#29

Trenz Electronic FPGA Modules / Re: Flash QSPI TE0820 with 202...

Last post by Adrien - February 12, 2024, 03:42:56 PM

I happened to have other products from Trenz. I just tried with TE0820-05-4AE81MA REV5 and a carrier TE0703-05 this time and it works, first try. I am still using Xilinx 2022.2 tools on Windows 10 and the switch on the carrier is configured the same. I just did the same, launch _create_win_setup.cmd, create binaries, create zynqmp_fsbl (TE modified) with sw_libs/ and prebuilt .xsa file. I just don't know. If I have time I will test on the previous setup.

#30

Trenz Electronic FPGA Modules / Re: Flash QSPI TE0820 with 202...

Last post by JH - February 12, 2024, 08:00:49 AM

Hi,
here are some information about this topic:
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=105689937

At the end you should change boot mode to JTAG for flash programming, if you want to use newer Vivado version.Workaround with special FSBL seems to work less and less with each newer Version...

So simple install oder Vivado Labtools version (best was 17.2 as long as it now the device and the flash) and try again.
Or change boot mode to JTAG (there are different ways possible, depending on your carrier and CPLD Firmware). ways depends on CPLD Firmware, see CPLD Firmwar update and Variants:
https://wiki.trenz-electronic.de/display/PD/TE0820+CPLD+Firmware

Of course, it is also possible that the FSBL has a problem and simply crashes (FSBL does not match variant or module defective or simply a power problem). But I can't say that with your information yet. You could first boot from the SD card and see if that works.

br
John