Recent Posts

11

Trenz Electronic FPGA Modules / Re: TEM0001-01A - UART transmission issues with the "test board" reference design

« Last post by Kilian Jahn on May 26, 2023, 01:46:04 PM »

Hello pmjobin ,
i am the one who build the design for this board. I downloaded the online zip file like you did and I check on my board the design via FlashProExpress programming, via Libero programming with and without recompiling and soft core updates. I could not reproduce your error.

Your Uart settings are right , but your error description brings to my mind that the Uart Terminal and the board are out of sync . Can you try a different Uart Terminal ? I tried SmartTTY and Softconsole , both worked fine on my board .

There are older Demo projects available . They are based on a different Hardware and Software Design .
Via " Download  ->  lab_guides  ->  archive " you will find everything that you need .
The guide "SMF2000_Cortex_M3_PWM_lab_guide_Lib2021d3_SC2021d3_v1.5.pdf "
explains it in great detail . Most interesting is the demo "RTC_time application" .

Regards Kilian

12

Trenz Electronic FPGA Modules / TE0790 under virtual box Ubuntu Guest

« Last post by pema on May 26, 2023, 11:17:19 AM »

Hi there,
this is most likely a issue caused by VirtualBox rather than the TE0790. But perhaps someone is experiencing the same issue and knows a work around.
Since I perform most of the development under a virtual machine, I would also like to have access to the JTAG probe under Linux virtual machine.

The problem:
When I connect the TE0790 to the VM I am able to connect through the xsdb or xsct but not able to list the targets( bellow you find the output).

Code: [Select]

ubuntu@ubuntu-VirtualBox:~$ lsusb
Bus 001 Device 003: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
Bus 001 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
ubuntu@ubuntu-VirtualBox:~$ xsdb
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.
                                                                                                                                             
****** System Debugger (XSDB) v2023.1
  **** Build date : May  7 2023-15:13:35
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.


xsdb% connect                                                                                                                                 
attempting to launch hw_server
                                                                                                                                             
****** Xilinx hw_server v2023.1
  **** Build date : May  7 2023 at 15:13:34
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application

INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121

tcfchan#0
xsdb% targets                                                                                                                                 
xsdb%      

Under Windows Host this does not happens:

Code: [Select]

C:\Xilinx\Vitis\2022.2\bin
λ .\xsct

****** Xilinx Software Commandline Tool (XSCT) v2022.2.0
  **** SW Build 0 on 2022-10-13-12:09:39
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.


xsct% connect
tcfchan#0
xsct% targets
  1  PS TAP
     2  PMU
     3  PL
  4  PSU
     5  RPU (Reset)
        6  Cortex-R5 #0 (RPU Reset)
        7  Cortex-R5 #1 (RPU Reset)
     8  APU (L2 Cache Reset)
        9  Cortex-A53 #0 (APU Reset)
       10  Cortex-A53 #1 (APU Reset)
xsct%
Anyone having the same issue? I can of course be always switching between VM and Host  to developt and flash or debug. But like I said is quite tedius to switch between both.

Greetings

13

Trenz Electronic FPGA Modules / Re: TE0820 Flash eMMC and/or QSPI over JTAG

« Last post by pema on May 24, 2023, 08:26:54 AM »

Many thanks! I will give it a try.

14

Trenz Electronic FPGA Modules / TEM0001-01A - UART transmission issues with the "test board" reference design

« Last post by pmjobin on May 23, 2023, 07:41:16 PM »

Hello,

I bought a SMF2000 FPGA module in early 2019 and just got around to trying it out. As a first step (after installing Libero 21.2 and before overwriting the factory image), I opened a serial terminal on the COM port (115200 bauds 8N1) that appeared after I connected the board to my PC in order to validate that the serial connection was working as intended, which it did. The message that was displayed in the terminal was a large "MICROSEMI" title followed by "Hello PolarFire! This is SmartFusion2.". I'm pointing this out in case it helps identifying the factory image that was present on my board.

Next, I programmed the "TEM0001_test-board_Libero-2021.2" reference design provided on your website using the FlashPro Express method outlined in the wiki. In other words, I did not rebuild the design, I merely took the image straight out of the archive and programmed it as is on the board. Since then, all the text that appears in the serial terminal is garbled. I tried playing with the COM port settings to no avail. I believe the image was programmed correctly because the led patterns operate as expected. I also managed to connect to the JTAG port and step through the code of the "HelloWorld" application in SoftConsole.

Before diving further, I would prefer to get the serial communication up and running with the reference design. Any suggestion as to what steps I should take next?

Regards,
P-M

15

MAX1000 community projects / Re: SD Ram Controller for MAX100

« Last post by Thomas D on May 23, 2023, 02:59:02 PM »

It is not listed in platform designer (e.g. 21.1 standard version). See also the attached screenshot (20.1.1 Standard <-> 21.1.1 Standard)

16

Trenz Electronic FPGA Modules / Re: TE0890 HyperRAM data corruption

« Last post by lasse@elcon.se on May 23, 2023, 01:24:04 PM »

Dear Antti,

is it possbily to get this ipcore with this fix. I have a custom board with artix-7 and two hyperrams on board to check if it works .

/Lasse

17

Trenz Electronic FPGA Modules / Re: TE0890 HyperRAM data corruption

« Last post by lasse@elcon.se on May 23, 2023, 12:19:56 PM »

I think this is good news.
So there is some problem with hyperram and short burst.

Maybe OpenHBMC has the same problem.

Good work.
/Lasse

18

Trenz Electronic FPGA Modules / Re: TE0820 Flash eMMC and/or QSPI over JTAG

« Last post by mch on May 22, 2023, 03:39:22 PM »

Hi,
I have answered your question via support Email.
Best regards
Mohsen

19

Trenz Electronic FPGA Modules / Re: TE0890 HyperRAM data corruption

« Last post by Antti Lukats on May 22, 2023, 03:22:45 PM »

another week of testing without errors.

just to be clear we test with CR00107 and ISSI hyperram die REV D

20

Trenz Electronic FPGA Modules / TE0820 Flash eMMC and/or QSPI over JTAG

« Last post by pema on May 22, 2023, 12:04:05 PM »

Hello there,
I am currently using the TE0820-03-03CG-1EA REV.3  together with the Carrier board TE0706-02.

For my project I need to flash the eMMC and QSPI over JTAG.
Under the CPLD firmware readme package are the following firmware options available:

Revision 04 for TE0820-03:
  -SC0820_REV03_qspi.jed -> QSPI or JTAG Boot Mode can be selected
  -SC0820_REV03_sd.jed  -> JTAG or SD Boot Mode can be selected
  -SC0820_REV03_qspi_sd.jed  -> QSPI or SD Boot Mode can be selected (default firmware)
  -SC0820_REV03_qspi_sd_jtag.jed  -> QSPI or SD Boot Mode or JTAG can be selected (JTAG selection over NOSEQ Pin, check carrier, if this can used)

And on the website are:

   
Available CPLD Firmware
TE0820 CPLD - Firmware description with different Variants for PCB REV03 and newer
        QSPI / SD /JTAG /eMMC Boot Modi - Default delivered, QSPI or SD Boot Mode is selectable via Boot Mode Pin and carrier depended PGOOD Pin can be used to select JTAG or eMMC Boot
        QSPI / JTAG Boot Modi - Use QSPI  or JTAG Boot Mode is selectable via Boot Mode Pin
        JTAG / SD Boot Modi - SD or JTAG Boot Mode is selectable via Boot Mode Pin
        QSPI / SD Boot Modi, QSPI or SD Boot Mode is selectable via Boot Mode Pin

From this I would be more interested in the first option: QSPI / SD /JTAG /eMMC Boot Modi (But here is the PGOOD pin used instead).

My question is what firmwares can I use and which signals (PGOOD / NOSEQ) are used or valid ?
And more important how can I make sure that they are working?
I would appreciate if you could shed any light on this topics.
Many thanks.