Recent Posts

Pages: [1] 2 3 ... 10
Trenz Electronic FPGA Modules / Re: TE0715 Multi-SPI
« Last post by benwefers on March 31, 2023, 07:10:35 PM »
So as an update, it seems the best approach for my original problem is just using GPIO to control the 4 chip selects. But now I have encountered a different problem.

I got a new board to test with and just to make sure the hardware was functioning correctly I flashed it over QSPI with an old Petalinux BOOT.bin that I have flashed on another board a dozen times. It flashed successfully, the Petalinux booted up just fine and everything worked as expected. I then attempted to flash it with a new version I created but immediately got an error "unrecognized JEDEC id bytes: 00, 00, 00". I then tried to flash it with the original version that I know works, but get the same error, though sometimes the numbers will change slightly.

Petalinux boots up fine still with the firmware I first flashed it with but it seems I have no way of changing it. With the other board I was able to reflash it over and over again with no issues, though that one was given to me so maybe something had been changed on it? Any ideas why this may be and how can I fix it?

UltraScale / Re: QSPI boot in AMP configuration for TE0808
« Last post by JH on March 30, 2023, 01:47:38 PM »
sorry we can't help much on this topic. Maybe it's better you ask also on AMD(Xilinx) forum, because this is independent from trenz module and other forum has bigger community.

AMD has also documentation (also for newer Vivado versions like it looks) regarding this topic:

there are also information here:

Trenz Electronic FPGA Modules / Re: TE0720 - how to boot from QSPI with rootfs in flash
« Last post by JH on March 30, 2023, 01:43:35 PM »
this depends on the petalinux version....we have some older project where we have done this one time:

for details you must check AND(Xilinx) documentation for your petalinux version .
Trenz Electronic FPGA Modules / Re: TE0720 Ethernet to PL - IO placement error
« Last post by JH on March 30, 2023, 01:37:09 PM »
onboard eth phy is connected to MIO.  You can change controller to PL but not pcb connection.....PS configuration depends on HW configuration on the PCB!
 You can use TE0720 together with TE0706 carrier. TE0706 has separte Gbit ETH PHY which is accessible via PL...I think, that's what you need.
We have also an older demo design for this combination:
Hello all,

I have a working setup for my TE0720 + custom carrier board that currently is booting from a SD Card.

I would now like to change it so the system boots from QSPI and uses a rootfs on the flash.

Is there are information on how to do this?

Trenz Electronic FPGA Modules / Re: series 7 zynq board Serdes termination
« Last post by JH on March 29, 2023, 11:59:59 AM »
there are also 7 series zynq with HP Banks available.
TE0715 with Z030 assembled for example or TE0745...all a Zynq >= Z030 has HP IOs.
We have some table where you can check which Modules has HP IOs:
--> also as excel on the download area evailable.
Trenz Electronic FPGA Modules / series 7 zynq board Serdes termination
« Last post by cucchi on March 29, 2023, 03:22:21 AM »
I wanted to buy some of the Trenz Series 7 Zynq boards for a project. This will be attached to a camera with 18 pairs of LVDS25 signals. I noticed that the Trenz boards do not have a pad for them so I may make a termination. Since the Zynq has "HR" ports only and "DCI" is not available then how to I make the termination to the FPGA or is termination ok at the point on the connector mating from my camera board. Please advise, maybe I'm missing an aspect of the LVDS and I may need some education on this subject.
Best Regards
Daniel C.     ;D
UltraScale / QSPI boot in AMP configuration for TE0808
« Last post by peppeav82 on March 28, 2023, 05:11:43 PM »
I have a TE0808 equipped with 512M bits of Micron flash (JEDEC 0x20 0xBB 0x20). Boot mode is configured as QSPI 32bit/dual parallel/4 bit bus.
I worked with a 3 cores AMP solution (baremetal on 2 cores + FreeRTOS on 1 core) and everything worked perfectly until I had to add the fourth core (baremetal) to the whole configuration.
As soon as I add the fourth core to the boot image, the FSBL seems to hang immediately before the "Exit from FSBL" message, with all previous message all clean and without errors (Partition x Load Success, correct DDR address where to copy). I also would like to say that the application runs perfectly from RAM loaded via debugger SDK and JTAG.
I had a suspect on the size of the whole QSPI boot image, which was exceeding 32MBytes but I managed to reduce the whole image size to a 28MBytes size but results are still the same. I also can't find a solution to create a second stage bootloader (like u-boot) and try to overcome the problem.
I have nothing which can help in the debug, as the FSBL_DETAILED_INFO seems to return a long sequence of successes, only thing is that sometimes the board stucks at
Running Cpu Handoff address: 0x0, Exec State: 0
Other times the hang happens just one step after at
Exit from FSBL
Again, another maybe helping thing is that, when the FSBL hangs in that way, the board cannot be programmed again until I run a simple, single-core application through the JTAG, otherwise the JTAG itself will always fail from the SDK.

I have tried to generate boot image by aligning every partition to the flash page size (256), tried to delay the startup of each image manually with long sleeps, avoided the xil_printfs in the first stages, tried to invert the partition ordering, tried to shrink, but it seems that nothing except 4 hello worlds can be loaded from the QSPI and boot.

Sorry if the message seems too long or imprecise, I am really in a dead end and I cannot find a viable explaination or solution to my problem. I also cannot find a suitable u.boot prebuilt image to do other kind of experimentation.

Any help is welcomed.
Thanks in advance

Trenz Electronic FPGA Modules / Re: Support for SFP+ in TEF1002 PCIe carrier.
« Last post by esper on March 26, 2023, 02:01:51 PM »
I found this, which solves my question:

Best regards
Trenz Electronic FPGA Modules / Support for SFP+ in TEF1002 PCIe carrier.
« Last post by esper on March 25, 2023, 12:36:42 PM »
currently I'm planning to use the SFP+ connectivity in the TEF1002 (with a TE0820 board). I have seen in the schematics, that the SFP+ control signals goes directly to the CPLD (MAX10) in the TEF1002 board, and I have no further information about what does the CPLD with those signals, or how can I access to those signals from the Zynq device. In fact, the serial lines of the SPF+ module goes to the GTLine2 available on the Zynq, and can be directly connected to the GEM2 controller in the processing section.

Can anybody help me??

Best regards
Pages: [1] 2 3 ... 10