Hi,
I am using te0720-03-2IF module and trying to run petalinux 2018.2 on our board. I am able to successfully boot and have the uart console. Most of the peripherals work. I am having issue with our 'AXI UART16550 2.0' IP's. We are using 8 UART IP's in our PL connected to IRQ_F2P on the zynq PS. The same design I have also used with QNX where all the AXI UART IPs work without any problem, so I am sure that the vivado design is correct.
I have started with the reference petalinux project from trenz and then updated the hardware description using "petalinux-config --get-hw-description".
I have also updated the number of 16550 uarts in kernel to 8.
After building my project, I could also see that the uart entries are populated properly in the pl.dtsi file. I have also rechecked the system.dtb (converted to system.dts) and see that all the uarts are present. I am posting an example uart entry below
Serial_UARTs_axi_uart16550_2: serial@43c20000 {
clock-frequency = <100000000>;
clock-names = "s_axi_aclk";
clocks = <&misc_clk_0>;
compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
current-speed = <115200>;
device_type = "serial";
interrupt-names = "ip2intc_irpt";
interrupt-parent = <&intc>;
interrupts = <0 29 4>;
port-number = <6>;
reg = <0x43c20000 0x10000>;
reg-offset = <0x1000>;
reg-shift = <2>;
xlnx,external-xin-clk-hz = <0x17d7840>;
xlnx,external-xin-clk-hz-d = <0x19>;
xlnx,has-external-rclk = <0x0>;
xlnx,has-external-xin = <0x0>;
xlnx,is-a-16550 = <0x1>;
xlnx,s-axi-aclk-freq-hz-d = "100.0";
xlnx,use-modem-ports = <0x1>;
xlnx,use-user-ports = <0x1>;
};
Once booted, I see in dmesg that all uarts are probed at runtime and the drivers attached
root@fcc_te0720_project:~# dmesg | grep 16550
Serial: 8250/16550 driver, 8 ports, IRQ sharing disabled
43c50000.serial: ttyS0 at MMIO 0x43c51000 (irq = 53, base_baud = 6250000) is a 16550A
43c10000.serial: ttyS1 at MMIO 0x43c11000 (irq = 54, base_baud = 6250000) is a 16550A
43ca0000.serial: ttyS2 at MMIO 0x43ca1000 (irq = 55, base_baud = 6250000) is a 16550A
43cb0000.serial: ttyS3 at MMIO 0x43cb1000 (irq = 56, base_baud = 6250000) is a 16550A
43c70000.serial: ttyS4 at MMIO 0x43c71000 (irq = 57, base_baud = 6250000) is a 16550A
43c20000.serial: ttyS5 at MMIO 0x43c21000 (irq = 58, base_baud = 6250000) is a 16550A
43c40000.serial: ttyS6 at MMIO 0x43c41000 (irq = 59, base_baud = 6250000) is a 16550A
43c60000.serial: ttyS7 at MMIO 0x43c61000 (irq = 60, base_baud = 6250000) is a 16550A
The problem is that in /proc/interrupt I don't see any of the UART interrupts and doing a loop on RX and TX of the uart, I dont see any data coming
root@fcc_te0720_project:~# cat /proc/interrupts
CPU0 CPU1
16: 0 0 GIC-0 27 Edge gt
17: 0 0 GIC-0 43 Level ttc_clockevent
18: 67148 58283 GIC-0 29 Edge twd
19: 0 0 GIC-0 37 Level arm-pmu
20: 0 0 GIC-0 38 Level arm-pmu
21: 43 0 GIC-0 39 Level f8007100.adc
25: 0 0 GIC-0 57 Level cdns-i2c
26: 8 0 GIC-0 80 Level cdns-i2c
28: 0 0 GIC-0 35 Level f800c000.ocmc
29: 315 0 GIC-0 59 Level xuartps
30: 0 0 GIC-0 58 Level e0006000.spi
31: 9 0 GIC-0 51 Level e000d000.spi
32: 874 0 GIC-0 54 Level eth0
33: 0 0 GIC-0 77 Level eth1
34: 330 0 GIC-0 56 Level mmc0
35: 471 0 GIC-0 79 Level mmc1
36: 0 0 GIC-0 45 Level f8003000.dmac
37: 0 0 GIC-0 46 Level f8003000.dmac
38: 0 0 GIC-0 47 Level f8003000.dmac
39: 0 0 GIC-0 48 Level f8003000.dmac
40: 0 0 GIC-0 49 Level f8003000.dmac
41: 0 0 GIC-0 72 Level f8003000.dmac
42: 0 0 GIC-0 73 Level f8003000.dmac
43: 0 0 GIC-0 74 Level f8003000.dmac
44: 0 0 GIC-0 75 Level f8003000.dmac
45: 0 0 GIC-0 40 Level f8007000.devcfg
51: 0 0 GIC-0 53 Level e0002000.usb
52: 0 0 GIC-0 41 Edge f8005000.watchdog
IPI1: 0 0 Timer broadcast interrupts
IPI2: 41535 42405 Rescheduling interrupts
IPI3: 213 200 Function call interrupts
IPI4: 0 0 CPU stop interrupts
IPI5: 0 0 IRQ work interrupts
IPI6: 0 0 completion interrupts
Err: 0
I am not sure what I am missing. I would be very grateful if someone can help.
Best Regards,
Khizer
Hi,
sorry I didn't work with this IP from Xilinx until now. So I can't help much
What you ask is a more Xilinx specific question, maybe you should write your questions also on the Xilinx forum.
Or check for example:
https://forums.xilinx.com/t5/Embedded-Linux/UART-16550-not-seen-as-a-device-in-dev-in-Petalinux/td-p/1001421
--> maybe you has the same problem
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842080/AXI+UART+16550+standalone+driver
...
br
John
Hi,
Thank you for your reply.
I will post it on the Xilinx forum.
Best Regards,
Khizer