-------------------------------------------------- 1. Select your Board in "Board selection" area 2. Click "Create project" to generate the reference design from source files 3. To program device click "Program device" button: -> select between prebuilt file (if available) or other file -> use "Start program device" button to program device with selected file -> or open quartus programmer GUI with "Open quartus programmer" button 4. Open project in quartus prime GUI with the button "Open project" -------------------------------------------------- Info: [TE_TK-03] Selected Product ID: TEI0050-01-AAH13A Info: [TE_TK-10] Start creating project. Info: [TE_INIT-09] Board Part definition: Info: ::TE::ID: 1 Info: ::TE::PRODID: TEI0050-01-AAH13A Info: ::TE::FAMILY: Cyclone V Info: ::TE::DEVICE: 5CEBA2U15C8 Info: ::TE::SHORTNAME: AH13 Info: ::TE::FLASHTYP: W25Q64JV Info: ::TE::FLASH_SIZE: 8MB Info: ::TE::DDR_DEV: TEI0050_single_W9864G6JT-6 Info: ::TE::DDR_SIZE: 8MB Info: ::TE::PCB_REV: REV01 Info: ::TE::NOTES: NA Info: ------ Info: [TE_INIT-13] Use quartus source files from E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/source_files/quartus Info: [TE_INIT-14] Use software source files from E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/source_files/software Info: [TE_DES-2] Run TE::INIT::run_project 1 0 3 Info: [TE_UTILS-06] Clean project workspace Info: [TE_UTILS-09] E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus doesn't exist. Info: [TE_UTILS-10] Clean software workspace Info: [TE_UTILS-13] E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/software doesn't exist. Info: [TE_DES-25] Run build project (all). Please wait ... Info: [TE_QUART-13] Create empty project. Please wait ... Info: [TE_QUART-41] Create project without predefined pin assignments. Info: [TE_UTILS-34] Write board select info file ... Info: [TE_UTILS-35] Board select info file directory: E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/TEI0050-01-AAH13A.teinfo ------------------------------ Info: [TE_QUART-14] Create empty project -> done ------------------------------ Info: [TE_UTILS-26] Copy source files to project ... ------------------------------ Info: [TE_QUART-15] Execute test_board.tcl. It can take a few minutes, please wait ... Info: [TE_QUART-17] Execute test_board.tcl -> done ------------------------------ Info: [TE_QUART-01] Create NIOS_test_board.qsys. It can take a few minutes, please wait ... Info: [TE_QUART-02] Command results on: exec c:/intelfpga_lite/21.1/quartus/sopc_builder/bin/qsys-script.exe {--cmd=set ::args 5CEBA2U15C8|Cyclone\ V|TEI0050_single_W9864G6JT-6|hello_tei0050} --script=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board.tcl {--search-path=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/ip/**/*,E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/settings/*,$}: Info: Doing: qsys-script --cmd=set ::args 5CEBA2U15C8|Cyclone\ V|TEI0050_single_W9864G6JT-6|hello_tei0050 --script=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board.tcl --search-path=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/ip/**/*,E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/settings/*,$ Info: create_system NIOS_test_board Info: set_project_property DEVICE_FAMILY Cyclone V Info: set_project_property DEVICE 5CEBA2U15C8 Info: set_project_property HIDE_FROM_IP_CATALOG false Info: add_instance clk clock_source 21.1 Info: set_instance_parameter_value clk clockFrequency 50000000.0 Info: set_instance_parameter_value clk clockFrequencyKnown 1 Info: set_instance_parameter_value clk resetSynchronousEdges NONE Info: add_instance nios2 altera_nios2_gen2 21.1 Info: set_instance_parameter_value nios2 bht_ramBlockType Automatic Info: set_instance_parameter_value nios2 breakOffset 32 Info: set_instance_parameter_value nios2 breakSlave None Info: set_instance_parameter_value nios2 cdx_enabled 0 Info: set_instance_parameter_value nios2 cpuArchRev 1 Info: set_instance_parameter_value nios2 cpuID 0 Info: set_instance_parameter_value nios2 cpuReset 0 Info: set_instance_parameter_value nios2 data_master_high_performance_paddr_base 0 Info: set_instance_parameter_value nios2 data_master_high_performance_paddr_size 0.0 Info: set_instance_parameter_value nios2 data_master_paddr_base 0 Info: set_instance_parameter_value nios2 data_master_paddr_size 0.0 Info: set_instance_parameter_value nios2 dcache_bursts false Info: set_instance_parameter_value nios2 dcache_numTCDM 0 Info: set_instance_parameter_value nios2 dcache_ramBlockType Automatic Info: set_instance_parameter_value nios2 dcache_size 2048 Info: set_instance_parameter_value nios2 dcache_tagramBlockType Automatic Info: set_instance_parameter_value nios2 dcache_victim_buf_impl ram Info: set_instance_parameter_value nios2 debug_OCIOnchipTrace _128 Info: set_instance_parameter_value nios2 debug_assignJtagInstanceID 0 Info: set_instance_parameter_value nios2 debug_datatrigger 0 Info: set_instance_parameter_value nios2 debug_debugReqSignals 0 Info: set_instance_parameter_value nios2 debug_enabled 1 Info: set_instance_parameter_value nios2 debug_hwbreakpoint 0 Info: set_instance_parameter_value nios2 debug_jtagInstanceID 0 Info: set_instance_parameter_value nios2 debug_traceStorage onchip_trace Info: set_instance_parameter_value nios2 debug_traceType none Info: set_instance_parameter_value nios2 debug_triggerArming 1 Info: set_instance_parameter_value nios2 dividerType no_div Info: set_instance_parameter_value nios2 exceptionOffset 32 Info: set_instance_parameter_value nios2 exceptionSlave sdram_controller.s1 Info: set_instance_parameter_value nios2 fa_cache_line 2 Info: set_instance_parameter_value nios2 fa_cache_linesize 0 Info: set_instance_parameter_value nios2 flash_instruction_master_paddr_base 0 Info: set_instance_parameter_value nios2 flash_instruction_master_paddr_size 0.0 Info: set_instance_parameter_value nios2 icache_burstType None Info: set_instance_parameter_value nios2 icache_numTCIM 0 Info: set_instance_parameter_value nios2 icache_ramBlockType Automatic Info: set_instance_parameter_value nios2 icache_size 4096 Info: set_instance_parameter_value nios2 icache_tagramBlockType Automatic Info: set_instance_parameter_value nios2 impl Tiny Info: set_instance_parameter_value nios2 instruction_master_high_performance_paddr_base 0 Info: set_instance_parameter_value nios2 instruction_master_high_performance_paddr_size 0.0 Info: set_instance_parameter_value nios2 instruction_master_paddr_base 0 Info: set_instance_parameter_value nios2 instruction_master_paddr_size 0.0 Info: set_instance_parameter_value nios2 io_regionbase 0 Info: set_instance_parameter_value nios2 io_regionsize 0 Info: set_instance_parameter_value nios2 master_addr_map 0 Info: set_instance_parameter_value nios2 mmu_TLBMissExcOffset 0 Info: set_instance_parameter_value nios2 mmu_TLBMissExcSlave None Info: set_instance_parameter_value nios2 mmu_autoAssignTlbPtrSz 1 Info: set_instance_parameter_value nios2 mmu_enabled 0 Info: set_instance_parameter_value nios2 mmu_processIDNumBits 8 Info: set_instance_parameter_value nios2 mmu_ramBlockType Automatic Info: set_instance_parameter_value nios2 mmu_tlbNumWays 16 Info: set_instance_parameter_value nios2 mmu_tlbPtrSz 7 Info: set_instance_parameter_value nios2 mmu_udtlbNumEntries 6 Info: set_instance_parameter_value nios2 mmu_uitlbNumEntries 4 Info: set_instance_parameter_value nios2 mpu_enabled 0 Info: set_instance_parameter_value nios2 mpu_minDataRegionSize 12 Info: set_instance_parameter_value nios2 mpu_minInstRegionSize 12 Info: set_instance_parameter_value nios2 mpu_numOfDataRegion 8 Info: set_instance_parameter_value nios2 mpu_numOfInstRegion 8 Info: set_instance_parameter_value nios2 mpu_useLimit 0 Info: set_instance_parameter_value nios2 mpx_enabled 0 Info: set_instance_parameter_value nios2 mul_32_impl 2 Info: set_instance_parameter_value nios2 mul_64_impl 0 Info: set_instance_parameter_value nios2 mul_shift_choice 0 Info: set_instance_parameter_value nios2 ocimem_ramBlockType Automatic Info: set_instance_parameter_value nios2 ocimem_ramInit 0 Info: set_instance_parameter_value nios2 regfile_ramBlockType Automatic Info: set_instance_parameter_value nios2 register_file_por 0 Info: set_instance_parameter_value nios2 resetOffset 1441792 Info: set_instance_parameter_value nios2 resetSlave serial_flash_ctrl.avl_mem Info: set_instance_parameter_value nios2 resetrequest_enabled 1 Info: set_instance_parameter_value nios2 setting_HBreakTest 0 Info: set_instance_parameter_value nios2 setting_HDLSimCachesCleared 1 Info: set_instance_parameter_value nios2 setting_activateMonitors 1 Info: set_instance_parameter_value nios2 setting_activateTestEndChecker 0 Info: set_instance_parameter_value nios2 setting_activateTrace 0 Info: set_instance_parameter_value nios2 setting_allow_break_inst 0 Info: set_instance_parameter_value nios2 setting_alwaysEncrypt 1 Info: set_instance_parameter_value nios2 setting_asic_add_scan_mode_input 0 Info: set_instance_parameter_value nios2 setting_asic_enabled 0 Info: set_instance_parameter_value nios2 setting_asic_synopsys_translate_on_off 0 Info: set_instance_parameter_value nios2 setting_asic_third_party_synthesis 0 Info: set_instance_parameter_value nios2 setting_avalonDebugPortPresent 0 Info: set_instance_parameter_value nios2 setting_bhtPtrSz 8 Info: set_instance_parameter_value nios2 setting_bigEndian 0 Info: set_instance_parameter_value nios2 setting_branchpredictiontype Dynamic Info: set_instance_parameter_value nios2 setting_breakslaveoveride 0 Info: set_instance_parameter_value nios2 setting_clearXBitsLDNonBypass 1 Info: set_instance_parameter_value nios2 setting_dc_ecc_present 1 Info: set_instance_parameter_value nios2 setting_disable_tmr_inj 0 Info: set_instance_parameter_value nios2 setting_disableocitrace 0 Info: set_instance_parameter_value nios2 setting_dtcm_ecc_present 1 Info: set_instance_parameter_value nios2 setting_ecc_present 0 Info: set_instance_parameter_value nios2 setting_ecc_sim_test_ports 0 Info: set_instance_parameter_value nios2 setting_exportHostDebugPort 0 Info: set_instance_parameter_value nios2 setting_exportPCB 0 Info: set_instance_parameter_value nios2 setting_export_large_RAMs 0 Info: set_instance_parameter_value nios2 setting_exportdebuginfo 0 Info: set_instance_parameter_value nios2 setting_exportvectors 0 Info: set_instance_parameter_value nios2 setting_fast_register_read 0 Info: set_instance_parameter_value nios2 setting_ic_ecc_present 1 Info: set_instance_parameter_value nios2 setting_interruptControllerType Internal Info: set_instance_parameter_value nios2 setting_itcm_ecc_present 1 Info: set_instance_parameter_value nios2 setting_mmu_ecc_present 1 Info: set_instance_parameter_value nios2 setting_oci_export_jtag_signals 0 Info: set_instance_parameter_value nios2 setting_oci_version 1 Info: set_instance_parameter_value nios2 setting_preciseIllegalMemAccessException 0 Info: set_instance_parameter_value nios2 setting_removeRAMinit 0 Info: set_instance_parameter_value nios2 setting_rf_ecc_present 1 Info: set_instance_parameter_value nios2 setting_shadowRegisterSets 0 Info: set_instance_parameter_value nios2 setting_showInternalSettings 0 Info: set_instance_parameter_value nios2 setting_showUnpublishedSettings 0 Info: set_instance_parameter_value nios2 setting_support31bitdcachebypass 1 Info: set_instance_parameter_value nios2 setting_tmr_output_disable 0 Info: set_instance_parameter_value nios2 setting_usedesignware 0 Info: set_instance_parameter_value nios2 shift_rot_impl 1 Info: set_instance_parameter_value nios2 tightly_coupled_data_master_0_paddr_base 0 Info: set_instance_parameter_value nios2 tightly_coupled_data_master_0_paddr_size 0.0 Info: set_instance_parameter_value nios2 tightly_coupled_data_master_1_paddr_base 0 Info: set_instance_parameter_value nios2 tightly_coupled_data_master_1_paddr_size 0.0 Info: set_instance_parameter_value nios2 tightly_coupled_data_master_2_paddr_base 0 Info: set_instance_parameter_value nios2 tightly_coupled_data_master_2_paddr_size 0.0 Info: set_instance_parameter_value nios2 tightly_coupled_data_master_3_paddr_base 0 Info: set_instance_parameter_value nios2 tightly_coupled_data_master_3_paddr_size 0.0 Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_0_paddr_base 0 Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_0_paddr_size 0.0 Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_1_paddr_base 0 Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_1_paddr_size 0.0 Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_2_paddr_base 0 Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_2_paddr_size 0.0 Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_3_paddr_base 0 Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_3_paddr_size 0.0 Info: set_instance_parameter_value nios2 tmr_enabled 0 Info: set_instance_parameter_value nios2 tracefilename Info: set_instance_parameter_value nios2 userDefinedSettings Info: add_instance pll altera_pll 21.1 Info: set_instance_parameter_value pll debug_print_output 0 Info: set_instance_parameter_value pll debug_use_rbc_taf_method 0 Info: set_instance_parameter_value pll gui_active_clk 0 Info: set_instance_parameter_value pll gui_actual_output_clock_frequency0 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency1 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency10 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency11 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency12 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency13 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency14 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency15 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency16 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency17 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency2 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency3 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency4 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency5 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency6 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency7 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency8 0 MHz Info: set_instance_parameter_value pll gui_actual_output_clock_frequency9 0 MHz Info: set_instance_parameter_value pll gui_actual_phase_shift0 0 Info: set_instance_parameter_value pll gui_actual_phase_shift1 0 Info: set_instance_parameter_value pll gui_actual_phase_shift10 0 Info: set_instance_parameter_value pll gui_actual_phase_shift11 0 Info: set_instance_parameter_value pll gui_actual_phase_shift12 0 Info: set_instance_parameter_value pll gui_actual_phase_shift13 0 Info: set_instance_parameter_value pll gui_actual_phase_shift14 0 Info: set_instance_parameter_value pll gui_actual_phase_shift15 0 Info: set_instance_parameter_value pll gui_actual_phase_shift16 0 Info: set_instance_parameter_value pll gui_actual_phase_shift17 0 Info: set_instance_parameter_value pll gui_actual_phase_shift2 0 Info: set_instance_parameter_value pll gui_actual_phase_shift3 0 Info: set_instance_parameter_value pll gui_actual_phase_shift4 0 Info: set_instance_parameter_value pll gui_actual_phase_shift5 0 Info: set_instance_parameter_value pll gui_actual_phase_shift6 0 Info: set_instance_parameter_value pll gui_actual_phase_shift7 0 Info: set_instance_parameter_value pll gui_actual_phase_shift8 0 Info: set_instance_parameter_value pll gui_actual_phase_shift9 0 Info: set_instance_parameter_value pll gui_cascade_counter0 0 Info: set_instance_parameter_value pll gui_cascade_counter1 0 Info: set_instance_parameter_value pll gui_cascade_counter10 0 Info: set_instance_parameter_value pll gui_cascade_counter11 0 Info: set_instance_parameter_value pll gui_cascade_counter12 0 Info: set_instance_parameter_value pll gui_cascade_counter13 0 Info: set_instance_parameter_value pll gui_cascade_counter14 0 Info: set_instance_parameter_value pll gui_cascade_counter15 0 Info: set_instance_parameter_value pll gui_cascade_counter16 0 Info: set_instance_parameter_value pll gui_cascade_counter17 0 Info: set_instance_parameter_value pll gui_cascade_counter2 0 Info: set_instance_parameter_value pll gui_cascade_counter3 0 Info: set_instance_parameter_value pll gui_cascade_counter4 0 Info: set_instance_parameter_value pll gui_cascade_counter5 0 Info: set_instance_parameter_value pll gui_cascade_counter6 0 Info: set_instance_parameter_value pll gui_cascade_counter7 0 Info: set_instance_parameter_value pll gui_cascade_counter8 0 Info: set_instance_parameter_value pll gui_cascade_counter9 0 Info: set_instance_parameter_value pll gui_cascade_outclk_index 0 Info: set_instance_parameter_value pll gui_channel_spacing 0.0 Info: set_instance_parameter_value pll gui_clk_bad 0 Info: set_instance_parameter_value pll gui_device_speed_grade 1 Info: set_instance_parameter_value pll gui_divide_factor_c0 1 Info: set_instance_parameter_value pll gui_divide_factor_c1 1 Info: set_instance_parameter_value pll gui_divide_factor_c10 1 Info: set_instance_parameter_value pll gui_divide_factor_c11 1 Info: set_instance_parameter_value pll gui_divide_factor_c12 1 Info: set_instance_parameter_value pll gui_divide_factor_c13 1 Info: set_instance_parameter_value pll gui_divide_factor_c14 1 Info: set_instance_parameter_value pll gui_divide_factor_c15 1 Info: set_instance_parameter_value pll gui_divide_factor_c16 1 Info: set_instance_parameter_value pll gui_divide_factor_c17 1 Info: set_instance_parameter_value pll gui_divide_factor_c2 1 Info: set_instance_parameter_value pll gui_divide_factor_c3 1 Info: set_instance_parameter_value pll gui_divide_factor_c4 1 Info: set_instance_parameter_value pll gui_divide_factor_c5 1 Info: set_instance_parameter_value pll gui_divide_factor_c6 1 Info: set_instance_parameter_value pll gui_divide_factor_c7 1 Info: set_instance_parameter_value pll gui_divide_factor_c8 1 Info: set_instance_parameter_value pll gui_divide_factor_c9 1 Info: set_instance_parameter_value pll gui_divide_factor_n 1 Info: set_instance_parameter_value pll gui_dps_cntr C0 Info: set_instance_parameter_value pll gui_dps_dir Positive Info: set_instance_parameter_value pll gui_dps_num 1 Info: set_instance_parameter_value pll gui_dsm_out_sel 1st_order Info: set_instance_parameter_value pll gui_duty_cycle0 50 Info: set_instance_parameter_value pll gui_duty_cycle1 50 Info: set_instance_parameter_value pll gui_duty_cycle10 50 Info: set_instance_parameter_value pll gui_duty_cycle11 50 Info: set_instance_parameter_value pll gui_duty_cycle12 50 Info: set_instance_parameter_value pll gui_duty_cycle13 50 Info: set_instance_parameter_value pll gui_duty_cycle14 50 Info: set_instance_parameter_value pll gui_duty_cycle15 50 Info: set_instance_parameter_value pll gui_duty_cycle16 50 Info: set_instance_parameter_value pll gui_duty_cycle17 50 Info: set_instance_parameter_value pll gui_duty_cycle2 50 Info: set_instance_parameter_value pll gui_duty_cycle3 50 Info: set_instance_parameter_value pll gui_duty_cycle4 50 Info: set_instance_parameter_value pll gui_duty_cycle5 50 Info: set_instance_parameter_value pll gui_duty_cycle6 50 Info: set_instance_parameter_value pll gui_duty_cycle7 50 Info: set_instance_parameter_value pll gui_duty_cycle8 50 Info: set_instance_parameter_value pll gui_duty_cycle9 50 Info: set_instance_parameter_value pll gui_en_adv_params 0 Info: set_instance_parameter_value pll gui_en_dps_ports 0 Info: set_instance_parameter_value pll gui_en_phout_ports 0 Info: set_instance_parameter_value pll gui_en_reconf 0 Info: set_instance_parameter_value pll gui_enable_cascade_in 0 Info: set_instance_parameter_value pll gui_enable_cascade_out 0 Info: set_instance_parameter_value pll gui_enable_mif_dps 0 Info: set_instance_parameter_value pll gui_feedback_clock Global Clock Info: set_instance_parameter_value pll gui_frac_multiply_factor 1.0 Info: set_instance_parameter_value pll gui_fractional_cout 32 Info: set_instance_parameter_value pll gui_mif_generate 0 Info: set_instance_parameter_value pll gui_multiply_factor 1 Info: set_instance_parameter_value pll gui_number_of_clocks 3 Info: set_instance_parameter_value pll gui_operation_mode direct Info: set_instance_parameter_value pll gui_output_clock_frequency0 50.0 Info: set_instance_parameter_value pll gui_output_clock_frequency1 150.0 Info: set_instance_parameter_value pll gui_output_clock_frequency10 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency11 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency12 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency13 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency14 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency15 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency16 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency17 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency2 150.0 Info: set_instance_parameter_value pll gui_output_clock_frequency3 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency4 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency5 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency6 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency7 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency8 100.0 Info: set_instance_parameter_value pll gui_output_clock_frequency9 100.0 Info: set_instance_parameter_value pll gui_phase_shift0 0 Info: set_instance_parameter_value pll gui_phase_shift1 0 Info: set_instance_parameter_value pll gui_phase_shift10 0 Info: set_instance_parameter_value pll gui_phase_shift11 0 Info: set_instance_parameter_value pll gui_phase_shift12 0 Info: set_instance_parameter_value pll gui_phase_shift13 0 Info: set_instance_parameter_value pll gui_phase_shift14 0 Info: set_instance_parameter_value pll gui_phase_shift15 0 Info: set_instance_parameter_value pll gui_phase_shift16 0 Info: set_instance_parameter_value pll gui_phase_shift17 0 Info: set_instance_parameter_value pll gui_phase_shift2 0 Info: set_instance_parameter_value pll gui_phase_shift3 0 Info: set_instance_parameter_value pll gui_phase_shift4 0 Info: set_instance_parameter_value pll gui_phase_shift5 0 Info: set_instance_parameter_value pll gui_phase_shift6 0 Info: set_instance_parameter_value pll gui_phase_shift7 0 Info: set_instance_parameter_value pll gui_phase_shift8 0 Info: set_instance_parameter_value pll gui_phase_shift9 0 Info: set_instance_parameter_value pll gui_phase_shift_deg0 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg1 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg10 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg11 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg12 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg13 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg14 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg15 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg16 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg17 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg2 -90.0 Info: set_instance_parameter_value pll gui_phase_shift_deg3 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg4 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg5 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg6 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg7 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg8 0.0 Info: set_instance_parameter_value pll gui_phase_shift_deg9 0.0 Info: set_instance_parameter_value pll gui_phout_division 1 Info: set_instance_parameter_value pll gui_pll_auto_reset Off Info: set_instance_parameter_value pll gui_pll_bandwidth_preset Auto Info: set_instance_parameter_value pll gui_pll_cascading_mode Create an adjpllin signal to connect with an upstream PLL Info: set_instance_parameter_value pll gui_pll_mode Integer-N PLL Info: set_instance_parameter_value pll gui_ps_units0 degrees Info: set_instance_parameter_value pll gui_ps_units1 degrees Info: set_instance_parameter_value pll gui_ps_units10 ps Info: set_instance_parameter_value pll gui_ps_units11 ps Info: set_instance_parameter_value pll gui_ps_units12 ps Info: set_instance_parameter_value pll gui_ps_units13 ps Info: set_instance_parameter_value pll gui_ps_units14 ps Info: set_instance_parameter_value pll gui_ps_units15 ps Info: set_instance_parameter_value pll gui_ps_units16 ps Info: set_instance_parameter_value pll gui_ps_units17 ps Info: set_instance_parameter_value pll gui_ps_units2 degrees Info: set_instance_parameter_value pll gui_ps_units3 ps Info: set_instance_parameter_value pll gui_ps_units4 ps Info: set_instance_parameter_value pll gui_ps_units5 ps Info: set_instance_parameter_value pll gui_ps_units6 ps Info: set_instance_parameter_value pll gui_ps_units7 ps Info: set_instance_parameter_value pll gui_ps_units8 ps Info: set_instance_parameter_value pll gui_ps_units9 ps Info: set_instance_parameter_value pll gui_refclk1_frequency 100.0 Info: set_instance_parameter_value pll gui_refclk_switch 0 Info: set_instance_parameter_value pll gui_reference_clock_frequency 12.0 Info: set_instance_parameter_value pll gui_switchover_delay 0 Info: set_instance_parameter_value pll gui_switchover_mode Automatic Switchover Info: set_instance_parameter_value pll gui_use_locked 0 Info: add_instance sdram_clock_crossing_bridge altera_avalon_mm_clock_crossing_bridge 21.1 Info: set_instance_parameter_value sdram_clock_crossing_bridge ADDRESS_UNITS SYMBOLS Info: set_instance_parameter_value sdram_clock_crossing_bridge ADDRESS_WIDTH 10 Info: set_instance_parameter_value sdram_clock_crossing_bridge COMMAND_FIFO_DEPTH 32 Info: set_instance_parameter_value sdram_clock_crossing_bridge DATA_WIDTH 32 Info: set_instance_parameter_value sdram_clock_crossing_bridge MASTER_SYNC_DEPTH 2 Info: set_instance_parameter_value sdram_clock_crossing_bridge MAX_BURST_SIZE 1 Info: set_instance_parameter_value sdram_clock_crossing_bridge RESPONSE_FIFO_DEPTH 32 Info: set_instance_parameter_value sdram_clock_crossing_bridge SLAVE_SYNC_DEPTH 2 Info: set_instance_parameter_value sdram_clock_crossing_bridge SYMBOL_WIDTH 8 Info: set_instance_parameter_value sdram_clock_crossing_bridge USE_AUTO_ADDRESS_WIDTH 1 Info: add_instance sdram_controller altera_avalon_new_sdram_controller 21.1 Info: apply_preset sdram_controller TEI0050_single_W9864G6JT-6 Info: add_instance serial_flash_ctrl altera_epcq_controller2 21.1 Info: set_instance_parameter_value serial_flash_ctrl CHIP_SELS 1 Info: set_instance_parameter_value serial_flash_ctrl DDASI 0 Info: set_instance_parameter_value serial_flash_ctrl FLASH_TYPE EPCQ64A Info: set_instance_parameter_value serial_flash_ctrl IO_MODE QUAD Info: add_instance uart altera_avalon_uart 21.1 Info: set_instance_parameter_value uart baud 115200 Info: set_instance_parameter_value uart dataBits 8 Info: set_instance_parameter_value uart fixedBaud 1 Info: set_instance_parameter_value uart parity NONE Info: set_instance_parameter_value uart simCharStream Info: set_instance_parameter_value uart simInteractiveInputEnable 0 Info: set_instance_parameter_value uart simInteractiveOutputEnable 0 Info: set_instance_parameter_value uart simTrueBaud 0 Info: set_instance_parameter_value uart stopBits 1 Info: set_instance_parameter_value uart syncRegDepth 2 Info: set_instance_parameter_value uart useCtsRts 0 Info: set_instance_parameter_value uart useEopRegister 0 Info: set_instance_parameter_value uart useRelativePathForSimFile 0 Info: add_interface clk clock sink Info: set_interface_property clk EXPORT_OF clk.clk_in Info: add_interface reset reset sink Info: set_interface_property reset EXPORT_OF clk.clk_in_reset Info: add_interface sdram conduit end Info: set_interface_property sdram EXPORT_OF sdram_controller.wire Info: add_interface sdram_clk clock source Info: set_interface_property sdram_clk EXPORT_OF pll.outclk2 Info: add_interface uart conduit end Info: set_interface_property uart EXPORT_OF uart.external_connection Info: add_connection clk.clk pll.refclk Info: add_connection clk.clk_reset nios2.reset Info: add_connection clk.clk_reset pll.reset Info: add_connection clk.clk_reset sdram_clock_crossing_bridge.m0_reset Info: add_connection clk.clk_reset sdram_clock_crossing_bridge.s0_reset Info: add_connection clk.clk_reset sdram_controller.reset Info: add_connection clk.clk_reset serial_flash_ctrl.reset Info: add_connection clk.clk_reset uart.reset Info: add_connection nios2.data_master nios2.debug_mem_slave Info: set_connection_parameter_value nios2.data_master/nios2.debug_mem_slave arbitrationPriority 1 Info: set_connection_parameter_value nios2.data_master/nios2.debug_mem_slave baseAddress 0x02000800 Info: set_connection_parameter_value nios2.data_master/nios2.debug_mem_slave defaultConnection 0 Info: add_connection nios2.data_master sdram_clock_crossing_bridge.s0 Info: set_connection_parameter_value nios2.data_master/sdram_clock_crossing_bridge.s0 arbitrationPriority 1 Info: set_connection_parameter_value nios2.data_master/sdram_clock_crossing_bridge.s0 baseAddress 0x0000 Info: set_connection_parameter_value nios2.data_master/sdram_clock_crossing_bridge.s0 defaultConnection 0 Info: add_connection nios2.data_master serial_flash_ctrl.avl_csr Info: set_connection_parameter_value nios2.data_master/serial_flash_ctrl.avl_csr arbitrationPriority 1 Info: set_connection_parameter_value nios2.data_master/serial_flash_ctrl.avl_csr baseAddress 0x02001040 Info: set_connection_parameter_value nios2.data_master/serial_flash_ctrl.avl_csr defaultConnection 0 Info: add_connection nios2.data_master serial_flash_ctrl.avl_mem Info: set_connection_parameter_value nios2.data_master/serial_flash_ctrl.avl_mem arbitrationPriority 1 Info: set_connection_parameter_value nios2.data_master/serial_flash_ctrl.avl_mem baseAddress 0x01800000 Info: set_connection_parameter_value nios2.data_master/serial_flash_ctrl.avl_mem defaultConnection 0 Info: add_connection nios2.data_master uart.s1 Info: set_connection_parameter_value nios2.data_master/uart.s1 arbitrationPriority 1 Info: set_connection_parameter_value nios2.data_master/uart.s1 baseAddress 0x020010a0 Info: set_connection_parameter_value nios2.data_master/uart.s1 defaultConnection 0 Info: add_connection nios2.debug_reset_request nios2.reset Info: add_connection nios2.debug_reset_request pll.reset Info: add_connection nios2.debug_reset_request sdram_clock_crossing_bridge.m0_reset Info: add_connection nios2.debug_reset_request sdram_clock_crossing_bridge.s0_reset Info: add_connection nios2.debug_reset_request sdram_controller.reset Info: add_connection nios2.debug_reset_request serial_flash_ctrl.reset Info: add_connection nios2.debug_reset_request uart.reset Info: add_connection nios2.instruction_master nios2.debug_mem_slave Info: set_connection_parameter_value nios2.instruction_master/nios2.debug_mem_slave arbitrationPriority 1 Info: set_connection_parameter_value nios2.instruction_master/nios2.debug_mem_slave baseAddress 0x02000800 Info: set_connection_parameter_value nios2.instruction_master/nios2.debug_mem_slave defaultConnection 0 Info: add_connection nios2.instruction_master sdram_clock_crossing_bridge.s0 Info: set_connection_parameter_value nios2.instruction_master/sdram_clock_crossing_bridge.s0 arbitrationPriority 1 Info: set_connection_parameter_value nios2.instruction_master/sdram_clock_crossing_bridge.s0 baseAddress 0x0000 Info: set_connection_parameter_value nios2.instruction_master/sdram_clock_crossing_bridge.s0 defaultConnection 0 Info: add_connection nios2.instruction_master serial_flash_ctrl.avl_csr Info: set_connection_parameter_value nios2.instruction_master/serial_flash_ctrl.avl_csr arbitrationPriority 1 Info: set_connection_parameter_value nios2.instruction_master/serial_flash_ctrl.avl_csr baseAddress 0x02001040 Info: set_connection_parameter_value nios2.instruction_master/serial_flash_ctrl.avl_csr defaultConnection 0 Info: add_connection nios2.instruction_master serial_flash_ctrl.avl_mem Info: set_connection_parameter_value nios2.instruction_master/serial_flash_ctrl.avl_mem arbitrationPriority 1 Info: set_connection_parameter_value nios2.instruction_master/serial_flash_ctrl.avl_mem baseAddress 0x01800000 Info: set_connection_parameter_value nios2.instruction_master/serial_flash_ctrl.avl_mem defaultConnection 0 Info: add_connection nios2.instruction_master uart.s1 Info: set_connection_parameter_value nios2.instruction_master/uart.s1 arbitrationPriority 1 Info: set_connection_parameter_value nios2.instruction_master/uart.s1 baseAddress 0x020010a0 Info: set_connection_parameter_value nios2.instruction_master/uart.s1 defaultConnection 0 Info: add_connection nios2.irq serial_flash_ctrl.interrupt_sender Info: set_connection_parameter_value nios2.irq/serial_flash_ctrl.interrupt_sender irqNumber 1 Info: add_connection nios2.irq uart.irq Info: set_connection_parameter_value nios2.irq/uart.irq irqNumber 0 Info: add_connection pll.outclk0 nios2.clk Info: add_connection pll.outclk0 sdram_clock_crossing_bridge.s0_clk Info: add_connection pll.outclk0 serial_flash_ctrl.clock_sink Info: add_connection pll.outclk0 uart.clk Info: add_connection pll.outclk1 sdram_clock_crossing_bridge.m0_clk Info: add_connection pll.outclk1 sdram_controller.clk Info: add_connection sdram_clock_crossing_bridge.m0 sdram_controller.s1 Info: set_connection_parameter_value sdram_clock_crossing_bridge.m0/sdram_controller.s1 arbitrationPriority 1 Info: set_connection_parameter_value sdram_clock_crossing_bridge.m0/sdram_controller.s1 baseAddress 0x0000 Info: set_connection_parameter_value sdram_clock_crossing_bridge.m0/sdram_controller.s1 defaultConnection 0 Info: set_interconnect_requirement $system qsys_mm.clockCrossingAdapter HANDSHAKE Info: set_interconnect_requirement $system qsys_mm.enableEccProtection FALSE Info: set_interconnect_requirement $system qsys_mm.insertDefaultSlave FALSE Info: set_interconnect_requirement $system qsys_mm.maxAdditionalLatency 1 Info: auto_assign_system_base_addresses Info: save_system NIOS_test_board.qsys Info: [TE_QUART-03] Create NIOS_test_board.qsys -> done ------------------------------ Info: [TE_QUART-04] Generate NIOS_test_board.qsys. It can take a few minutes, please wait ... Info: [TE_QUART-05] Command results on: exec c:/intelfpga_lite/21.1/quartus/sopc_builder/bin/qsys-generate.exe E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board.qsys --synthesis=vhdl -bsf {--search-path=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/**/*,E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/settings/*,$}: Info: Saving generation log to E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board/NIOS_test_board_generation.rpt Info: Starting: Create block symbol file (.bsf) Info: qsys-generate E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\quartus\NIOS_test_board.qsys --block-symbol-file --output-directory=E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\quartus\NIOS_test_board --family="Cyclone V" --part=5CEBA2U15C8 Info: Loading quartus/NIOS_test_board.qsys Info: Reading input file Info: Adding clk [clock_source 21.1] Info: Parameterizing module clk Info: Adding nios2 [altera_nios2_gen2 21.1] Info: Parameterizing module nios2 Info: Adding pll [altera_pll 21.1] Info: Parameterizing module pll Info: Adding sdram_clock_crossing_bridge [altera_avalon_mm_clock_crossing_bridge 21.1] Info: Parameterizing module sdram_clock_crossing_bridge Info: Adding sdram_controller [altera_avalon_new_sdram_controller 21.1] Info: Parameterizing module sdram_controller Info: Adding serial_flash_ctrl [altera_epcq_controller2 21.1] Info: Parameterizing module serial_flash_ctrl Info: Adding uart [altera_avalon_uart 21.1] Info: Parameterizing module uart Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: NIOS_test_board.pll: The legal reference clock frequency is 5.0 MHz..650.0 MHz Info: NIOS_test_board.pll: Able to implement PLL with user settings Info: NIOS_test_board.sdram_controller: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Info: Starting: Create HDL design files for synthesis Info: qsys-generate E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\quartus\NIOS_test_board.qsys --synthesis=VHDL --output-directory=E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\quartus\NIOS_test_board\synthesis --family="Cyclone V" --part=5CEBA2U15C8 Info: Loading quartus/NIOS_test_board.qsys Info: Reading input file Info: Adding clk [clock_source 21.1] Info: Parameterizing module clk Info: Adding nios2 [altera_nios2_gen2 21.1] Info: Parameterizing module nios2 Info: Adding pll [altera_pll 21.1] Info: Parameterizing module pll Info: Adding sdram_clock_crossing_bridge [altera_avalon_mm_clock_crossing_bridge 21.1] Info: Parameterizing module sdram_clock_crossing_bridge Info: Adding sdram_controller [altera_avalon_new_sdram_controller 21.1] Info: Parameterizing module sdram_controller Info: Adding serial_flash_ctrl [altera_epcq_controller2 21.1] Info: Parameterizing module serial_flash_ctrl Info: Adding uart [altera_avalon_uart 21.1] Info: Parameterizing module uart Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: NIOS_test_board.pll: The legal reference clock frequency is 5.0 MHz..650.0 MHz Info: NIOS_test_board.pll: Able to implement PLL with user settings Info: NIOS_test_board.sdram_controller: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release. Info: NIOS_test_board: Generating NIOS_test_board "NIOS_test_board" for QUARTUS_SYNTH Info: Interconnect is inserted between master sdram_clock_crossing_bridge.m0 and slave sdram_controller.s1 because the master has readdata signal 32 bit wide, but the slave is 16 bit wide. Info: Interconnect is inserted between master sdram_clock_crossing_bridge.m0 and slave sdram_controller.s1 because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide. Info: Interconnect is inserted between master sdram_clock_crossing_bridge.m0 and slave sdram_controller.s1 because the master has writedata signal 32 bit wide, but the slave is 16 bit wide. Info: Interconnect is inserted between master sdram_clock_crossing_bridge.m0 and slave sdram_controller.s1 because the master has address signal 23 bit wide, but the slave is 22 bit wide. Info: Interconnect is inserted between master sdram_clock_crossing_bridge.m0 and slave sdram_controller.s1 because the master has byteenable signal 4 bit wide, but the slave is 2 bit wide. Info: Interconnect is inserted between master sdram_clock_crossing_bridge.m0 and slave sdram_controller.s1 because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide. Info: nios2: "NIOS_test_board" instantiated altera_nios2_gen2 "nios2" Info: pll: "NIOS_test_board" instantiated altera_pll "pll" Info: sdram_clock_crossing_bridge: "NIOS_test_board" instantiated altera_avalon_mm_clock_crossing_bridge "sdram_clock_crossing_bridge" Info: sdram_controller: Starting RTL generation for module 'NIOS_test_board_sdram_controller' Info: sdram_controller: Generation command is [exec C:/intelfpga_lite/21.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/21.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/21.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/21.1/quartus/../ip/altera/sopc_builder_ip/common -I ../altera_avalon_new_sdram_controller -- ../altera_avalon_new_sdram_controller/generate_rtl.pl --name=NIOS_test_board_sdram_controller --dir=C:/Users/stm/AppData/Local/Temp/alt9402_3528118557139864024.dir/0004_sdram_controller_gen/ --quartus_dir=C:/intelfpga_lite/21.1/quartus --verilog --config=C:/Users/stm/AppData/Local/Temp/alt9402_3528118557139864024.dir/0004_sdram_controller_gen//NIOS_test_board_sdram_controller_component_configuration.pl --do_build_sim=0 ] Info: sdram_controller: Done RTL generation for module 'NIOS_test_board_sdram_controller' Info: sdram_controller: "NIOS_test_board" instantiated altera_avalon_new_sdram_controller "sdram_controller" Info: serial_flash_ctrl: "NIOS_test_board" instantiated altera_epcq_controller2 "serial_flash_ctrl" Info: uart: Starting RTL generation for module 'NIOS_test_board_uart' Info: uart: Generation command is [exec C:/intelfpga_lite/21.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/21.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/21.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/21.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart -- C:/intelfpga_lite/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart/generate_rtl.pl --name=NIOS_test_board_uart --dir=C:/Users/stm/AppData/Local/Temp/alt9402_3528118557139864024.dir/0005_uart_gen/ --quartus_dir=C:/intelfpga_lite/21.1/quartus --verilog --config=C:/Users/stm/AppData/Local/Temp/alt9402_3528118557139864024.dir/0005_uart_gen//NIOS_test_board_uart_component_configuration.pl --do_build_sim=0 ] Info: uart: Done RTL generation for module 'NIOS_test_board_uart' Info: uart: "NIOS_test_board" instantiated altera_avalon_uart "uart" Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0 Info: mm_interconnect_0: "NIOS_test_board" instantiated altera_mm_interconnect "mm_interconnect_0" Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 Info: mm_interconnect_1: "NIOS_test_board" instantiated altera_mm_interconnect "mm_interconnect_1" Info: irq_mapper: "NIOS_test_board" instantiated altera_irq_mapper "irq_mapper" Info: rst_controller: "NIOS_test_board" instantiated altera_reset_controller "rst_controller" Info: cpu: Starting RTL generation for module 'NIOS_test_board_nios2_cpu' Info: cpu: Generation command is [exec C:/intelFPGA_lite/21.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/21.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/21.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/21.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/21.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/21.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/21.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/21.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=NIOS_test_board_nios2_cpu --dir=C:/Users/stm/AppData/Local/Temp/alt9402_3528118557139864024.dir/0008_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/21.1/quartus/bin64/ --verilog --config=C:/Users/stm/AppData/Local/Temp/alt9402_3528118557139864024.dir/0008_cpu_gen//NIOS_test_board_nios2_cpu_processor_configuration.pl --do_build_sim=0 ] Info: cpu: # 2023.02.14 20:34:02 (*) Starting Nios II generation Info: cpu: # 2023.02.14 20:34:02 (*) Elaborating CPU configuration settings Info: cpu: # 2023.02.14 20:34:02 (*) Creating all objects for CPU Info: cpu: # 2023.02.14 20:34:05 (*) Generating RTL from CPU objects Info: cpu: # 2023.02.14 20:34:05 (*) Creating plain-text RTL Info: cpu: # 2023.02.14 20:34:06 (*) Done Nios II generation Info: cpu: Done RTL generation for module 'NIOS_test_board_nios2_cpu' Info: cpu: "nios2" instantiated altera_nios2_gen2_unit "cpu" Info: asmi2_inst_epcq_ctrl: "serial_flash_ctrl" instantiated altera_asmi_parallel2 "asmi2_inst_epcq_ctrl" Info: addr_adaption_0: "serial_flash_ctrl" instantiated altera_qspi_address_adaption "addr_adaption_0" Info: nios2_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_data_master_translator" Info: serial_flash_ctrl_avl_csr_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "serial_flash_ctrl_avl_csr_translator" Info: nios2_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_data_master_agent" Info: serial_flash_ctrl_avl_csr_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "serial_flash_ctrl_avl_csr_agent" Info: serial_flash_ctrl_avl_csr_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "serial_flash_ctrl_avl_csr_agent_rsp_fifo" Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router" Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002" Info: serial_flash_ctrl_avl_mem_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "serial_flash_ctrl_avl_mem_burst_adapter" Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux" Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux" Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux" Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux" Info: Reusing file E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board/synthesis/submodules/altera_merlin_arbitrator.sv Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter" Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router" Info: router_001: "mm_interconnect_1" instantiated altera_merlin_router "router_001" Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux" Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux" Info: Reusing file E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board/synthesis/submodules/altera_merlin_arbitrator.sv Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux" Info: Reusing file E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board/synthesis/submodules/altera_merlin_arbitrator.sv Info: sdram_controller_s1_rsp_width_adapter: "mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_controller_s1_rsp_width_adapter" Info: Reusing file E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board/synthesis/submodules/altera_merlin_address_alignment.sv Info: Reusing file E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board/synthesis/submodules/altera_merlin_burst_uncompressor.sv Info: avalon_st_adapter: "mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter" Info: csr_controller: "asmi2_inst_epcq_ctrl" instantiated altera_asmi2_csr_controller "csr_controller" Info: avst_fifo: "Generating: avst_fifo" Info: xip_controller: "asmi2_inst_epcq_ctrl" instantiated altera_asmi2_xip_controller "xip_controller" Info: merlin_demultiplexer_0: "asmi2_inst_epcq_ctrl" instantiated altera_merlin_demultiplexer "merlin_demultiplexer_0" Info: multiplexer: "asmi2_inst_epcq_ctrl" instantiated altera_merlin_multiplexer "multiplexer" Info: Reusing file E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board/synthesis/submodules/altera_merlin_arbitrator.sv Info: asmi2_cmd_generator_0: "asmi2_inst_epcq_ctrl" instantiated altera_asmi2_cmd_generator "asmi2_cmd_generator_0" Info: asmi2_qspi_interface_0: "asmi2_inst_epcq_ctrl" instantiated altera_asmi2_qspi_interface "asmi2_qspi_interface_0" Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" Info: avst_fifo: "xip_controller" instantiated altera_asmi2_xip_controller "avst_fifo" Info: NIOS_test_board: Done "NIOS_test_board" with 43 modules, 75 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: [TE_QUART-06] Generate NIOS_test_board.qsys -> done ------------------------------ Info: [TE_DES-37] Create software project 'hello_tei0050'. Please wait ... Info: [TE_SDK-01] Create software files. Please wait ... project: hello_tei0050 cpu-name: nios2 elf-name: hello_tei0050.elf Info: [TE_SDK-04] Create software files -> done ------------------------------ Info: [TE_SDK-05] Create bsp. Please wait ... Info: [TE_SDK-06] Command results on: exec wsl bash /mnt/c/intelfpga_lite/21.1/nios2eds/nios2_command_shell.sh ./create-this-bsp --no-make: create-this-bsp: Running "nios2-bsp hal E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/software/hello_tei0050_bsp/ E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board.sopcinfo --set hal.enable_small_c_library true --set hal.enable_c_plus_plus false --set hal.enable_reduced_device_drivers true --cpu-name nios2" nios2-bsp: Using /mnt/c/intelfpga_lite/21.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings. nios2-bsp: Creating new BSP because E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/software/hello_tei0050_bsp//settings.bsp doesn't exist. nios2-bsp: Running "nios2-bsp-create-settings.exe --sopc e:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board.sopcinfo --type hal --settings E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/software/hello_tei0050_bsp//settings.bsp --bsp-dir E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/software/hello_tei0050_bsp/ --script c:/intelfpga_lite/21.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl --set hal.enable_small_c_library true --set hal.enable_c_plus_plus false --set hal.enable_reduced_device_drivers true --cpu-name nios2" Info: Creating BSP settings file... Info: nios2-bsp-create-settings --sopc e:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/NIOS_test_board.sopcinfo --type hal --settings E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/software/hello_tei0050_bsp//settings.bsp --bsp-dir E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/software/hello_tei0050_bsp/ --script c:/intelfpga_lite/21.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl --set hal.enable_small_c_library true --set hal.enable_c_plus_plus false --set hal.enable_reduced_device_drivers true --cpu-name nios2 Info: Initializing SOPC project local software IP Info: [Info] E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/* matched 15 files in 0,01 seconds Info: [Info] E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/*/*_sw.tcl matched 0 files in 0,00 seconds Info: [Info] E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/ip/**/*_sw.tcl matched 0 files in 0,00 seconds Info: [Info] E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/ip/**/*_sw.tcl matched 0 files in 0,00 seconds Info: Finished initializing SOPC project local software IP. Total time taken = 2 seconds Info: Searching for BSP components with category: driver_element Info: Searching for BSP components with category: software_package_element Info: Found Flash Memory: serial_flash_ctrl_avl_mem for CPU: nios2 Info: Loading drivers from ensemble report. Info: Finished loading drivers from ensemble report. Info: Tcl message: "STDIO character device is uart" Info: Tcl message: "No system timer device" Info: Tcl message: "Default linker sections mapped to sdram_controller" Info: Tcl message: "Bootloader located at the reset address." Info: Tcl message: "Application ELF not allowed to contain code at the reset address." Info: Tcl message: "The alt_load() facility is disabled." Info: Default memory regions will not be persisted in BSP Settings File. Info: Generated file "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\settings.bsp" Info: BSP settings file was created at location "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\settings.bsp". Info: Generating BSP files... Info: Generating BSP files in "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\" Info: Default memory regions will not be persisted in BSP Settings File. Info: Generated file "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\settings.bsp" Info: Generated file "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\summary.html" Info: Generated file "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\linker.x" Info: Generated file "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\linker.h" Info: Generated file "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\memory.gdb" Info: Generated file "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\Makefile" Info: Generated file "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\mem_init.mk" Info: Generated file "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\system.h" Info: Generated file "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\public.mk" Info: Generated file "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp\alt_sys_init.c" Info: Finished generating BSP files. Total time taken = 2 seconds Info: BSP files generated in "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050_bsp" Info: [TE_SDK-07] Create bsp -> done ------------------------------ Info: [TE_SDK-08] Create app. Please wait ... Info: [TE_SDK-09] Command results on: exec wsl bash /mnt/c/intelfpga_lite/21.1/nios2eds/nios2_command_shell.sh ./create-this-app --no-make: create-this-app: Running "nios2-app-generate-makefile.exe --bsp-dir E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/software/hello_tei0050_bsp/ --set QUARTUS_PROJECT_DIR=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/ --elf-name hello_tei0050.elf --set OBJDUMP_INCLUDE_SOURCE 1 --src-files main.c" Info: nios2-app-generate-makefile --bsp-dir E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/software/hello_tei0050_bsp/ --set QUARTUS_PROJECT_DIR E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/ --elf-name hello_tei0050.elf --set OBJDUMP_INCLUDE_SOURCE 1 --src-files main.c Info: Generating application makefile Info: Generated file "E:\Users\stm\Documents\FPGA\Altera\test_board-quartus_21.1.1-new\software\hello_tei0050\Makefile" Info: Application makefile generated Info: [TE_SDK-10] Create app -> done ------------------------------ Info: [TE_SDK-11] Make all - software. Please wait ... Info: [TE_SDK-12] Command results on: exec wsl bash /mnt/c/intelfpga_lite/21.1/nios2eds/nios2_command_shell.sh make: Info: Building /mnt/e/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/software/hello_tei0050_bsp/ make --no-print-directory -C /mnt/e/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/software/hello_tei0050_bsp/ Compiling alt_alarm_start.c... nios2-elf-gcc.exe -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c make[1]: nios2-elf-gcc.exe: No such file or directory make[1]: *** [Makefile:564: obj/HAL/src/alt_alarm_start.o] Error 127 make: *** [Makefile:847: /mnt/e/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/software/hello_tei0050_bsp/-recurs-make-lib] Error 2 Info: [TE_SDK-13] Make all - software -> done ------------------------------ Info: [TE_SDK-14] Generate hex file. Please wait ... Info: [TE_SDK-17] Command results on: exec wsl bash /mnt/c/intelfpga_lite/21.1/nios2eds/nios2_command_shell.sh elf2hex.exe hello_tei0050.elf 0x00000000 0x007fffff --width=16 --little-endian-mem --create-lanes=0 mem_init/sdram_controller.hex: Error: java.io.FileNotFoundException: hello_tei0050.elf (Das System kann die angegebene Datei nicht finden) Info: [TE_SDK-15] Command results on: exec wsl bash /mnt/c/intelfpga_lite/21.1/nios2eds/nios2_command_shell.sh elf2flash.exe --base=0x01800000 --end=0x01ffffff --reset=0x01960000 --input=hello_tei0050.elf --output=mem_init/serial_flash_ctrl.flash --boot=c:/intelfpga_lite/21.1/quartus/../nios2eds/components/altera_nios2/boot_loader_cfi.srec: Error: java.io.FileNotFoundException: hello_tei0050.elf (Das System kann die angegebene Datei nicht finden) Info: [TE_SDK-16] Command results on: exec wsl bash /mnt/c/intelfpga_lite/21.1/nios2eds/nios2_command_shell.sh nios2-elf-objcopy.exe -I srec -O ihex mem_init/serial_flash_ctrl.flash mem_init/serial_flash_ctrl.hex: /mnt/c/intelfpga_lite/21.1/nios2eds/nios2_command_shell.sh: line 186: exec: nios2-elf-objcopy.exe: not found Info: [TE_SDK-18] Generate hex file -> done ------------------------------ Info: [TE_DES-43] Create software project 'hello_tei0050' -> done ----------------------------------------------------------------------- Info: [TE_QUART-10] Generate block symbol files. Please wait ... Info: [TE_QUART-11] Command results on: exec quartus_map --generate_symbol=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/ddrclk.vhd: Info: ******************************************************************* Info: Running Quartus Prime Create Symbol File Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition Info: Copyright (C) 2022 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Feb 14 20:35:04 2023 Info: Command: quartus_map --generate_symbol=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/ddrclk.vhd Info: Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4742 megabytes Info: Processing ended: Tue Feb 14 20:35:06 2023 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 Info: [TE_QUART-11] Command results on: exec quartus_map --generate_symbol=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/hdl/case_state_seq.vhd: Info: ******************************************************************* Info: Running Quartus Prime Create Symbol File Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition Info: Copyright (C) 2022 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Feb 14 20:35:07 2023 Info: Command: quartus_map --generate_symbol=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/hdl/case_state_seq.vhd Info: Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4742 megabytes Info: Processing ended: Tue Feb 14 20:35:08 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Info: [TE_QUART-11] Command results on: exec quartus_map --generate_symbol=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/hdl/control_mux.vhd: Info: ******************************************************************* Info: Running Quartus Prime Create Symbol File Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition Info: Copyright (C) 2022 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Feb 14 20:35:09 2023 Info: Command: quartus_map --generate_symbol=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/hdl/control_mux.vhd Info: Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4742 megabytes Info: Processing ended: Tue Feb 14 20:35:10 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Info: [TE_QUART-11] Command results on: exec quartus_map --generate_symbol=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/hdl/pwm_seq.vhd: Info: ******************************************************************* Info: Running Quartus Prime Create Symbol File Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition Info: Copyright (C) 2022 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Feb 14 20:35:11 2023 Info: Command: quartus_map --generate_symbol=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/hdl/pwm_seq.vhd Info: Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4742 megabytes Info: Processing ended: Tue Feb 14 20:35:13 2023 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 Info: [TE_QUART-11] Command results on: exec quartus_map --generate_symbol=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/hdl/shift_reg_seq.vhd: Info: ******************************************************************* Info: Running Quartus Prime Create Symbol File Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition Info: Copyright (C) 2022 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Feb 14 20:35:13 2023 Info: Command: quartus_map --generate_symbol=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/hdl/shift_reg_seq.vhd Info: Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4742 megabytes Info: Processing ended: Tue Feb 14 20:35:15 2023 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 Info: [TE_QUART-12] Generate block symbol files -> done ------------------------------ Info: [TE_QUART-07] Regenerate IP Cores. Please wait ... Info: [TE_QUART-08] Command results on: exec mw-regenerate.exe --project_directory=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus: Info: ******************************************************************* Info: Running Quartus Prime IP Upgrade Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition Info: Copyright (C) 2022 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Feb 14 20:35:16 2023 Info: Command: mw-regenerate --project_directory=E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus Info: (11837): Started upgrading IP component with file ""E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/ddrclk.vhd"" Info: (11131): Completed upgrading IP component with file ""E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/ddrclk.vhd"" Info: Quartus Prime IP Upgrade was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4599 megabytes Info: Processing ended: Tue Feb 14 20:35:30 2023 Info: Elapsed time: 00:00:14 Info: Total CPU time (on all processors): 00:00:00 Info: [TE_QUART-09] Regenerate IP Cores -> done ------------------------------ Info: [TE_QUART-18] Compile project. It can take a few minutes, please wait ... Info: [TE_QUART-20] Compile project -> done ------------------------------ Info: [TE_QUART-25] Generate test_board.jic file. Please wait ... Info: [TE_QUART-26] Command results on: exec quartus_cpf.exe -c E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/conv_setup.cof: Info: ******************************************************************* Info: Running Quartus Prime Convert_programming_file Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition Info: Copyright (C) 2022 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Feb 14 20:43:10 2023 Info: Command: quartus_cpf -c E:/Users/stm/Documents/FPGA/Altera/test_board-quartus_21.1.1-new/quartus/conv_setup.cof Info: (210033): Memory Map File ./output_files/test_board.map contains memory usage information for file ./output_files/test_board.jic Error: (17923): Can't save or open file ../software/hello_tei0050/mem_init/serial_flash_ctrl.hex Info: [TE_QUART-27] Generate test_board.jic file. -> done ------------------------------ Info: [TE_DES-36] Run build project (all) -> done ----------------------------------------------------------------------- Info: [TE_DES-19] Run project finished with 860 infos, 0 warnings, 0 critical warnings, 3 errors. -----------------------------------------------------------------------