Recent posts

#21

Open source hardware / Re: TE0726-04 ZynqBerry + zhdm...

Last post by zerkman - November 06, 2024, 12:34:50 AM

I rewrote the HDMI constraints as follows, specifying all n and p pins.
From the schematic I also noticed the clock p and n pins are swapped, but I'm leaving the original order for now.
I only swapped the d_p[ 0 ] and d_n[ 0 ] as instructed.

Code Select Expand

# HDMI
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_tx_clk_p hdmi_tx_clk_n}]
set_property PACKAGE_PIN R7 [get_ports hdmi_tx_clk_p]
set_property PACKAGE_PIN R8 [get_ports hdmi_tx_clk_n]

set_property IOSTANDARD TMDS_33 [get_ports {hdmi_tx_d_p[*] hdmi_tx_d_n[*]}]
set_property PACKAGE_PIN P9 [get_ports {hdmi_tx_d_p[0]}]
set_property PACKAGE_PIN P8 [get_ports {hdmi_tx_d_n[0]}]
set_property PACKAGE_PIN P10 [get_ports {hdmi_tx_d_p[1]}]
set_property PACKAGE_PIN R10 [get_ports {hdmi_tx_d_n[1]}]
set_property PACKAGE_PIN P11 [get_ports {hdmi_tx_d_p[2]}]
set_property PACKAGE_PIN R11 [get_ports {hdmi_tx_d_n[2]}]

Now, Vivado produces this error on write_bitstream:

ERROR: [DRC UCIO-1] Unconstrained Logical Port: 2 out of 43 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: hdmi_tx_d_p[0], and hdmi_tx_d_n[0].

Please note that I also previously got the same error when trying to swap the n and p in the top level design. Similarly I got errors when trying to invert (NOT operator) the output values of d_p[ 0 ] and d_n[ 0 ].

I could set the SEVERITY to Warning as explained in the error message, but I assume my problem is not about unspecified pin locations (they are set correctly in the xdc) so I would not want to do something dangerous.

As explained above the clock p and n bits also seem to be swapped; if I swap the R7/R8 pin assignments in the xdc, this results in 4 port assigment issues (the previous ones plus the clock p and n ports) instead of 2.

#22

Trenz Electronic FPGA Modules / Re: TE0701-06 Assembly Diagram...

Last post by M.Tserabei - November 05, 2024, 03:18:27 PM

Hi, we updated assembly diagram. Best regards, Maksim Tserabei

#23

Open source hardware / Re: TE0726-04 ZynqBerry + zhdm...

Last post by RC - November 04, 2024, 02:30:04 PM

Hi,

The Swap is for the optimal PCB routing. Otherwise,the routing would be complicated. Could you modify the XDC file and manually assign all the pins(n and p)? It might be a simpler workaround.

#24

Trenz Electronic FPGA Modules / Re: Detecting wrong speed grad...

Last post by neels - October 31, 2024, 06:57:34 PM

Thanks Mohsen, I have sent a request to the support email address regarding the CPLD source code.

regards,
Neels

#25

UltraScale / TEB0818+TE00813 custom hardwar...

Last post by marcelobraga - October 31, 2024, 01:00:14 PM

I'm following the AMD guide for developping a device driver for a custom axi IP: https://docs.amd.com/r/en-US/ug1165-zynq-embedded-design-tutorial/Creating-Custom-IP-and-Device-Drivers-for-Linux as well as the one for deploying a custom Petalinux image for the Trenz board.

However I'm having problems during petalinux-build command, it seems it only builds when my Vivado block design has the same ZynqMP configuration as in the Trenz StarterKit or TestBoard examples. Whenever I try to to create a hardware platform in VIvado from scratch, without all the configs for the ZynqMP, my petalinux-build fail.

Is this how it is supposed to happen? I can provide any log files if necessary

#26

Trenz Electronic FPGA Modules / Re: Detecting wrong speed grad...

Last post by mch - October 31, 2024, 09:25:55 AM

Hi,

please send your request for the CPLD source code to our support Email address. ( support@trenz-electronic.de)

I will send you the old and new CPLD source code. You can either use old code or modify new code to store speed_grade, temperature_grade and model numbers.

Best regards,

Mohsen

#27

Trenz Electronic FPGA Modules / Re: Detecting wrong speed grad...

Last post by neels - October 28, 2024, 04:28:53 PM

Hi John,

Thanks again for the detailed answer and for the useful pointers.

It was really useful to have the  speed_grade, temperature_grade and model numbers in the EEPROM and being read by the FSBL. As a user, I could reliably track the module, chip and its features. It is unfortunate that these features are no longer available in CPLD Revision 07. But I can also understand your point in terms of managing multiple variants of the boards.

It would be really useful if Trenz can program the serial number of the device, and some of the above information in the EEPROM (like how Xilinx does for its SOM) at Factory, so that users can have a visibility to what module is being used. Just a suggestion from my end.

Regarding 3), its good that  CPLD Revision 07 code is backward compatible. I wanted to know if the source code is available for CPLD (can only see .jed files) ? and if any of the registers on phy can be repurposed to store the board information (by the user writing into it using phytool). In this way I can have a custom solution to interpret the board info and solve my problem.   

#28

Open source hardware / Re: TE0726-04 ZynqBerry + zhdm...

Last post by zerkman - October 28, 2024, 03:11:12 PM

Sorry I meant hdmi_tx_d_p[ 0 ] and and hdmi_tx_d_n[ 0 ] are swapped.

#29

Open source hardware / Re: TE0726-04 ZynqBerry + zhdm...

Last post by zerkman - October 28, 2024, 03:06:35 PM

After further investigation, it appears the hdmi_tx_d_p

• and hdmi_tx_d_n
• output ports (blue component) are physically swapped.

I worked around the issue by inverting the input data bits for the TMDS serialiser of the blue component, and now I'm getting correct image and sound. No idea if it can easily be fixed on the Xilinx HDMI IP core.

Is it a known issue on the TE0726? Maybe only on revision 4?

#30

Trenz Electronic FPGA Modules / Re: Detecting wrong speed grad...

Last post by JH - October 28, 2024, 12:35:14 PM

Hi,
new FSBL code was introduced with 22.2 and newer,
you can check for example 23.2 version:
https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0720/Reference_Design/2023.2/test_board/TE0720-test_board-vivado_2023.2-build_4_20240124111006.zip

--> test_board\sw_lib\sw_apps\zynq_fsbl\src\ te_fsbl_hooks_te0720.c

Code Select Expand

    // Read register 4
    Status = XEmacPs_PhyRead(&Emac, 0x1A,  4, &rval16); if(Status != XST_SUCCESS){ return XST_FAILURE; }

    cpld_rev = (rval16 & 0x00FF);
    if (cpld_rev <= 6)
    {
        speed_grade = (rval16 >> 14) & 3;
        /* 0=C, 1=E, 2=I, 3=A */
        if ((rval16 & 0x3000)==0x0000) { temp_grade = 0x43; }
        else if ((rval16 & 0x3000)==0x1000) { temp_grade = 0x45; }
        else if ((rval16 & 0x3000)==0x2000) { temp_grade = 0x49; }
        else if ((rval16 & 0x3000)==0x3000) { temp_grade = 0x41; }
        else { temp_grade = 0x20; }

        if ((rval16 & 0x0F00)==0x000) { model1 = 0x20;model2 = 0x20;model3 = 0x46; }
        else if ((rval16 & 0x0F00)==0x100) { model1 = 0x20;model2 = 0x20;model3 = 0x52; }
        else if ((rval16 & 0x0F00)==0x200) { model1 = 0x20;model2 = 0x4C;model3 = 0x46; }
        else if ((rval16 & 0x0F00)==0x300) { model1 = 0x31;model2 = 0x34;model3 = 0x53; }
        else { model1 = 0x31;model2 = 0x31;model3 = 0x31; }


        xil_printf("\n\rSoM: TE0720-0%d-%d%c%c%c%c SC REV:%02x", pcb_rev, speed_grade, temp_grade, model1, model2, model3, rval16 & 0xFF);
        xil_printf("\n\rMAC: ");

        for(i = 0; i < 6; i++) {
        xil_printf("%02x ", mac_addr[i]);
        }
        xil_printf("\n\r");
    }
    else
    {
        Status = XEmacPs_PhyRead(&Emac, 0x1A,  4, &rval16); if(Status != XST_SUCCESS){ return XST_FAILURE; }
        wdt = (rval16 >> 14) & 0x3;
        if (wdt == 0b00)
        {
            wdt_status = "Deactive";
        }else if (wdt == 0b01)
        {
            wdt_status = "Hardware_WDT";
        }else if (wdt == 0b10)
        {
            wdt_status = "Software_WDT";
        }else if (wdt == 0b11)
        {
            wdt_status = "No WDT chip on the board. SOftware_WDT with PL clock";
        }
       
       
       
        boot_gen = (rval16 >> 12) & 0x3;
        if (boot_gen == 0b00)
        {
            bootmode_gen = "QSPI/SD";
        }else if (boot_gen == 0b01)
        {
            bootmode_gen = "QSPI/JTAG";
        }else if (boot_gen == 0b10)
        {
            bootmode_gen = "JTAG/SD";
        }else if (boot_gen == 0b11)
        {
            bootmode_gen = "default QSPI/JTAG/SD";
        }else
        {
            bootmode_gen = "undefined";
        }


        pudc = (rval16 >> 11) & 0x1;
        if (pudc==1)
        {
            pudc_mode = "Pulldown";
        } else
        {
            pudc_mode = "Pullup";
        }


        Status = XEmacPs_PhyRead(&Emac, 0x1A,  4, &rval16); if(Status != XST_SUCCESS){ return XST_FAILURE; }
        cpld_bm = (rval16 >> 10)& 0x01;
        if (cpld_bm == 0)
        {
            cpld_bootmode = "Deactive";
            // Read register 4
            Status = XEmacPs_PhyRead(&Emac, 0x1A,  4, &rval16); if(Status != XST_SUCCESS){ return XST_FAILURE; }
            boot = (rval16 >> 8) & 0x3;
            if (boot == 0b00)
            {
                boot_mode = "JTAG";
            }
            else if (boot == 0b10)
            {           
                boot_mode = "QSPI";
            }
            else if (boot == 0b11)
            {
                boot_mode = "SD Card";
            }
            else if (boot == 0b01)
            {
                boot_mode = "undefined";               
            }
            // xil_printf("\n\rSoM: TE0720 CPLD_BM=%s(%x) BOOTMOD_GEN=%x(%s) PUDC_MODE=%s(%d) BOOT_MODE=%s(%x) CPLD_REV=%02x", cpld_bootmode, cpld_bm, boot_gen, bootmode_gen, pudc_mode, pudc, boot_mode, boot, cpld_rev);
            // xil_printf("\n\rSoM: TE0720 WDT_STATUS=%s(%x) CPLD_BM=%s(%x) BOOTMOD_GEN=%x(%s) PUDC_MODE=%s(%d) BOOT_MODE=%s(%x) CPLD_REV=%02x", wdt_status, wdt, cpld_bootmode, cpld_bm, boot_gen, bootmode_gen, pudc_mode, pudc, boot_mode, boot, cpld_rev);
            xil_printf("\n\rCPLD_REV=%02x\n\r",cpld_rev);
            xil_printf("\n\rWDT_STATUS=%s(%x)\n\r", wdt_status,wdt);
            xil_printf("\n\rCPLD_BM=%s(%x)\n\r",cpld_bootmode, cpld_bm);
            xil_printf("\n\rBOOTMOD_GEN=%x(%s)\n\r", boot_gen, bootmode_gen);
            xil_printf("\n\rPUDC_MODE=%s(%d)\n\r", pudc_mode, pudc);
            xil_printf("\n\rBOOT_MODE=%s(%x)\n\r", boot_mode, boot);       
        } else
        {
            cpld_bootmode="Active";
            // Read register 12 (CR4[15:8])
            Status = XEmacPs_PhyRead(&Emac, 0x1A,  12, &rval16); if(Status != XST_SUCCESS){ return XST_FAILURE; }   
            boot = (rval16 >> 8) & 0x3;
            if (boot == 0b01)
            {
                boot_mode = "JTAG";
            }
            else if (boot == 0b10)
            {           
                boot_mode = "QSPI";
            }
            else if (boot == 0b11)
            {
                boot_mode = "SD Card";
            }
            else if (boot == 0b00)
            {
                boot_mode = "undefined";               
            }               
            // xil_printf("\n\rSoM: TE0720 CPLD_BM=%s(%x) BOOTMOD_GEN=%x(%s) PUDC_MODE=%s(%d) BOOT_MODE=%s(%x) CPLD_REV=%02x", cpld_bootmode, cpld_bm, boot_gen, bootmode_gen, pudc_mode, pudc, boot_mode, boot, cpld_rev);
            // xil_printf("\n\rSoM: TE0720 WDT_STATUS=%s(%x) CPLD_BM=%s(%x) BOOTMOD_GEN=%x(%s) PUDC_MODE=%s(%d) BOOT_MODE=%s(%x) CPLD_REV=%02x", wdt_status, wdt, cpld_bootmode, cpld_bm, boot_gen, bootmode_gen, pudc_mode, pudc, boot_mode, boot, cpld_rev);
            xil_printf("\n\rCPLD_REV=%02x\n\r",cpld_rev);
            xil_printf("\n\rWDT_STATUS=%s(%x)\n\r", wdt_status,wdt);
            xil_printf("\n\rCPLD_BM=%s(%x)\n\r",cpld_bootmode, cpld_bm);
            xil_printf("\n\rBOOTMOD_GEN=%x(%s)\n\r", boot_gen, bootmode_gen);
            xil_printf("\n\rPUDC_MODE=%s(%d)\n\r", pudc_mode, pudc);
            xil_printf("\n\rBOOT_MODE=%s(%x)\n\r", boot_mode, boot);
        }
                   
        xil_printf("\n\rMAC: ");
   
        for(i = 0; i < 6; i++) {
          xil_printf("%02x ", mac_addr[i]);
        }
        xil_printf("\n\r");
    }

regarding 2. Yes, because it's removed, now it shows CPLD revision, boot mode, WDT timer and PUDC configuration:
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-SCMDIOInterface
--> register 4

Brief background, in the past each TE0720 variant had its own CPLD code, therefore the variant name(with speed grade) was also stored there, as the number of variants increased, a standardized CPLD code for all variants was developed and the information removed with CPLD Revision 7

Regarding 3. CPLD Revision 07 code should be backward compatible with TE0720. Update Instructions
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD+Firmware
or did you mean update backward to have speed grade and temperature range on log again?

br
John