`timescale 1 ns/100 ps /*------------------------------------------------------------------------------- -- Title : Custom APB slave ------------------------------------------------------------------------------- -- File : reg_apb_wrp.v -- Author : Mir Ali -- Company : Microsemi Corporation -- Device : SmartFusion -- Standard : Verilog ------------------------------------------------------------------------------- -- Description: This code creates an APB slave wrapper on a 32x8 memory block(no wait state) -- It decodes the APB lite signals and then do the required action on the memory ------------------------------------------------------------------------------- -- Copyright (c) 2011 Microsemi Corporation -- All rights reserved. ------------------------------------------------------------------------------- -- Revisions : V2.0 -------------------------------------------------------------------------------*/ module reg_apb_wrp( input PCLK, input PENABLE, input PSEL, input PRESETN, input PWRITE, output PREADY, output PSLVERR, input [31:0] PADDR, input [31:0] PWDATA, output [31:0] PRDATA ); wire rd_enable; wire wr_enable; assign wr_enable = (PENABLE && PWRITE && PSEL); assign rd_enable = (!PWRITE && PSEL); //Data is ready during first cycle to make it availble on the bus when PENABLE is asserted assign PRDATA [ 31:8] = 24'h876543; reg16x8 reg16x8_0 (.clk(PCLK), .nreset(PRESETN), .wr_en(wr_enable), .rd_en(rd_enable), .addr(PADDR[3:0]), .data_in(PWDATA[7:0]), .data_out(PRDATA[7:0])); assign PREADY = 1'b1; assign PSLVERR = 1'b0; endmodule