Playing great new games:
https://itch.io/s/111036/full-pat-morita-pack
Capture playing Shovel Adventure:
https://youtu.be/uP6nl9aS-cw
New 4Mbytes Sdram to Sram Wrapper:
https://github.com/AtlasFPGA/zx/blob/main/atlas.max/sdram.v
New DVI/HDMI Wrapper in verilog:
https://github.com/AtlasFPGA/zx/blob/main/atlas.max/hdmi.v
And playing some new demos:
"Elysium State"
"In Color by Darklite and Offence"
Tutorial, how to port some VHDL opensource cores from reverse U16 - Spanish - you can use translation.
It is a great excersise to knwo how to deal with the VHDL program language and you can see it here.
In next videos I'm going to share how to deal with the serilizer, because MAX10, has a diferent serializer than cyc1000.
In this case i share the ZX48 implementation in VHDL as a .QAR proyect:
https://github.com/AtlasFPGA/U16_ZX_48_Spectrum_Reloj_50MHZ_VHDL