Recent posts

#21

UltraScale / TE0865-02+TEBT0865+KK0865

Last post by mer - June 04, 2025, 11:42:27 PM

Hello, beginning to put together as system utilizing TE0865-02+TEBT0865+KK0865. Noticing that the TEBT0865 TRM is empty. Am I looking in the wrong place? https://wiki.trenz-electronic.de/display/PD/TEBT0865
Also, there doesn't seem to be an obvious place to plug in the KK0865 pwm fan. Little help?

#22

UltraScale / Re: Support Request for TE0808...

Last post by JH - June 02, 2025, 08:50:31 AM

Hi,
bitstream itself does not configure PS. This will be done by FSBL, not with bitstream.This is the reason why you didn't see any VIO core, because CLK is missing. In case you want to use PS-PL CLKs and you need only PL part, boot system with your configured PS from SD Card (You can use our prebuilt Boot.bin in case you use the same CLKs like we in our reference design) and overwrite PL over JTAG like you has done above.
br
John

#23

Trenz Electronic FPGA Modules / Re: sys_clk IOSTANDARD for TE0...

Last post by bggardner - May 30, 2025, 05:45:23 PM

Thank you.  The sys_clk input (somehow) still works using LVCMOS33, but also works with your suggested changes.  For the benefit of others, I replaced

set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports sys_clk]

with

set_property INTERNAL_VREF 0.9 [get_iobanks 14]
set_property -dict {PACKAGE_PIN T14 IOSTANDARD SSTL18_I} [get_ports sys_clk]

#24

Trenz Electronic FPGA Modules / Re: sys_clk IOSTANDARD for TE0...

Last post by Antti Lukats - May 30, 2025, 12:07:53 PM

It is documentation XDC issue, please select SSTL18_I as IO Standard, after that you need open device constraints windows and use mouse to drop the IO Bank 14 to "0.9V" this will enable internal VREF.

Then it should work.

#25

UltraScale / Re: First "Hello World" - JTAG...

Last post by Antti Lukats - May 30, 2025, 11:32:07 AM

Hi Meik,

Please try downloading and installing the latest USB to JTAG converter driver from the manufacturer's website:

https://ftdichip.com/products/ft2232h-56q/

This may help resolve the JTAG-related issues you're experiencing.

I do not think that the issue is related to FTDI drivers. The JTAG seems to work OK.

#26

UltraScale / Re: Support Request for TE0808...

Last post by Antti Lukats - May 30, 2025, 11:30:36 AM

your report already says what the likely issue is, namly if the VIO core does not see a free running clock, it will not be detected. So it is a clocking issue.

#27

Trenz Electronic FPGA Modules / Re: Help Needed: Best Starter ...

Last post by Antti Lukats - May 30, 2025, 09:15:38 AM

The BEST is that you use our preferred method and download our reference design. You should use 2023.2 version. So you need update your Vivado. We have no support for 2023.1

PMOD is just 8 IO, what Advice you need about working with 8 IO pins?

Same for Clock, what advice are you looking? There are some options in the PS config in Vivado, and you can use PLL in the fabric to generate more clocks as needed.

#28

Trenz Electronic FPGA Modules / Help Needed: Best Starter Setu...

Last post by davidmillerdavid - May 29, 2025, 07:23:52 AM

Hi everyone,

I am fairly new to working with Trenz boards and recently got the TE0715-04-30-2C module. I am planning to use it with Vivado 2023.1 on a Windows 11 setup. I have been through the Trenz Wiki but wanted to ask directly here :-

What is the recommended starting point in terms of reference designs or precompiled projects for this board: ??

Do I need to customize the board files for Vivado 2023.1 or are the default ones on GitHub still good to go: ??

Any advice on working with the PMOD interfaces or clock config on this module: ??

Would really appreciate input from anyone who has hands-on experience with this board. Just want to make sure I am starting off with the right setup and avoid rookie mistakes.

Thanks in advance!!

With Regards,
David

azure course in bangalore

[System configuration:]

#29

UltraScale / Support Request for TE0808-05-...

Last post by cristina - May 28, 2025, 05:49:11 PM

Hi everyone ,

I'm facing an issue with the TE0808-05-BBE81-E board (Zynq UltraScale+ XCZU15EG-1FFVC900E, 4GB DDR4) and I would appreciate any help or guidance.

System configuration:
Board: TE0808-05-BBE81-E
Processor: Xilinx Zynq UltraScale+ XCZU15EG-1FFVC900E
Memory: 4 GB DDR4 SDRAM
Development environment: Vivado 2022.1

Workflow followed:
1-I downloaded the Starter Kit project for the TE0808 from the official Trenz Electronics website and imported it into Vivado.
2-Connected to the hardware using:
3-open_hw_manager
4-connect_hw_server -url localhost:3121 -allow_non_jtag
5-Detected the device with get_hw_devices xczu15_0
6-Generated the bitstream (zusys_wrapper.bit) and .ltx file (zusys_wrapper.ltx) through the implementation (impl_1)
7-Programmed the device using program_hw_devices

Main issue:
Although the bitstream is successfully loaded (DONE status = 1), Vivado does not detect the VIO visualization cores—specifically the vio_general core. As a result, I am unable to visualize any signals in the Hardware Manager, which is a critical part of my HIL validation process.
Given that I am using the official Starter Kit project downloaded from the Trenz Electronics website, I would expect it to work out-of-the-box.

Warnings
open_hw_manager
            connect_hw_server -url localhost:3121 -allow_non_jtag
            INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
            INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
            INFO: [Labtools 27-3414] Connected to existing cs_server.
            current_hw_target [get_hw_targets */xilinx_tcf/Digilent/2516330095A8A]
            set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/2516330095A8A]
            open_hw_target
            INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/2516330095A8A
            current_hw_device [get_hw_devices xczu15_0]
            refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xczu15_0] 0]
            INFO: [Labtools 27-1435] Device xczu15 (JTAG device index = 0) is not programmed (DONE status = 0).
            current_hw_device [get_hw_devices arm_dap_1]
            refresh_hw_device -update_hw_probes false [lindex [get_hw_devices arm_dap_1] 0]
            current_hw_device [get_hw_devices xczu15_0]
            reset_run impl_1 -prev_step
            launch_runs impl_1 -to_step write_bitstream -jobs 14
            [Wed May 21 11:33:39 2025] Launched impl_1...
            Run output will be captured here: C:/Users/c/Documents/StarterKitMain/StarterKit/vivado/StarterKit.runs/impl_1/runme.log
            set_property PROBES.FILE {C:/Users/c/MasterThesis/StarterKitMain/StarterKit/vivado/StarterKit.runs/impl_1/zusys_wrapper.ltx} [get_hw_devices xczu15_0]
            set_property FULL_PROBES.FILE {C:/Users/c/Documents/MasterThesis/StarterKitMain/StarterKit/vivado/StarterKit.runs/impl_1/zusys_wrapper.ltx} [get_hw_devices xczu15_0]
            set_property PROGRAM.FILE {C:/Users/c/Documents/MasterThesis/StarterKitMain/StarterKit/vivado/StarterKit.runs/impl_1/zusys_wrapper.bit} [get_hw_devices xczu15_0]
            program_hw_devices [get_hw_devices xczu15_0]
            INFO: [Labtools 27-3164] End of startup status: HIGH
            refresh_hw_device [lindex [get_hw_devices xczu15_0] 0]
            WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
            WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
            INFO: [Labtools 27-1434] Device xczu15 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
            WARNING: [Labtools 27-3361] The debug hub core was not detected.
            Resolution:
            1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
            For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'zusys_i/RGPIO/vio_rgpio' at location 'uuid_C549B3912D39530092A42F2FFB5AA883' from probes file, since it cannot be found on the programmed device.
            WARNING: [Labtools 27-3413] Dropping logic core with cellname:'zusys_i/vio_general' at location 'uuid_EB3ABBC93C055478BA1800E59EB82FB2' from probes file, since it cannot be found on the programmed device.

Has anyone faced this issue when using the official Starter Kit project from Trenz Electronics?
Is there a known fix or additional configuration required for proper VIO detection on the TE0808 board?

I'm attaching the block design diagram for reference.
Any help would be highly appreciated!

Thanks in advance!

#30

Trenz Electronic FPGA Modules / sys_clk IOSTANDARD for TE0714

Last post by bggardner - May 28, 2025, 04:32:29 PM

According to SCH-TE0714-04-42I-7-B.PDF, the 25MHz oscillator (U8) is powered by 1.8V.  The oscillator output is connected to B14_L13_P on Bank 14 (sys_clk in the board file), which is powered by VCCIO_0.  R21 connects VCCIO_0 to 3.3V, thereby making the IOSTANDARD for Bank 14 LVCMOS33.  However, LVCMOSS33 requires a minimum input-high voltage of 2.000V per AMD DS181, which the 1.8V-driven oscillator is unable to supply.  The TE0714_35_2I board file specifies sys_clk having IOSTANDARD LVCMOS33.  Is this an error with the schematic or otherwise unintended?