Hi,
I am using the TE020 in my application. The aim is, to load a new image in the QSPI flash and start it at run-time.
Therefore I would need to know the purpose of the BOOT_R and BOOT_R5 in the schematics: SCH-TE0720-03-1CR which are connected to the system controller CPLD.
Are these signals inputs to the CPLD, or could they have an impact if a QSPI boot is started at run-time?
Kind regards,
DG
Hi,
Boot Mode Pins, see also:
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
Default TE0720 support QSPI and SD Boot Mode, which can be selected with JM1-32:
https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Integration+Guide#id-4x5SoMIntegrationGuide-4x5ModuleControllerIOs
https://wiki.trenz-electronic.de/display/PD/TE0720+TRM#TE0720TRM-BootProcess
--> Program QSPI Flash with valid Boot.bin, set boot mode to QSPI and press reset button. In case you has a valid configuration it should reboot with your design on QSPI
br
John
Hi John,
thank you for your reply.
To put it in other words: these signals are only accessed by the CPLD at the start? Or is there any situation, in which these pins are again accessed later? Do they stay in high impedance mode? Since these signals seem to be used later for QSPIx4...
If I initiate a SOFT-RST (Zynq-Software), for example, reboot from a QSPI address which is not 0x0000 0000, should I be aware of any mechanisms started by the CPLD? In our application, we don't issue a hardware reset, via reset-button.
Thank you for your help!
Kind regards,
DG
Hi,
MIO which are used from QSPI has double functionality. At power up some of them are also used for boot mode, see:
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
page 166 table 6-4
CPLD control this pins only on power up to set boot mode. QSPI access itself is independent from CPLD.
br
John
Okay,
thank you very much!
Kind regards,
DG
Dear John,
I would have a follow-up question:
is there the possibility to issue a hardware reset of the QSPI over the BOOT_R5 signal.
Is there any signal, connecting CPLD and Zynq which can be used to request a hardware reset, coming from the Zynq and going to the CPLD?
Kind regards,
DG
Dear John,
I found the following:
https://wiki.trenz-electronic.de/display/PD/TE0720+System+Controller
Concerning to:
QuoteNew function: hard reset from PS Software
PS can force hard reset of itself (pulse on POR_B). This function is protected by enable signature that has to be written first. By default this functions is disabled.
New function: Hardware Watchdog.
This function is protected by enable signature that has to be written first. By default this functions is disabled. When watchdog is enabled then PS has to hit it periodically to prevent the Watchdog to generate a full hard reset (POR_B pulse).
But how is it used?
I also found the following:
https://wiki.trenz-electronic.de/display/PD/SPI+32+Bit+Addressing
Refering to solution #10, which resembles the hardware implementation with your external CPLD (system controller) on the TE0720: this leads to the same question. Can the Zynq issue a hard reset of the QSPI only, on the TE0720?
I have the impression, that the solution for my (obviously known) problem is somewhere hidden in your TRENZ Wiki, but I cannot find it. Please help me!
Kind regards,
DG
Hi
QSPI flash on TE0720 can not be hard-resetted by software - the RST pin is disable as the flash is in 4 bit mode.
BOOT_x pins are used at soc reset to latch the boot mode
br
Antti Lukats