Print Page - TE0890 Clock Input from Oscillator

Title: TE0890 Clock Input from Oscillator
Post by: flakmasta on June 24, 2020, 12:12:07 AM

Is it intentional that the 100MHz single-ended clock is not driven into the P side of an SRCC or MRCC pin?

Has anyone had issues with this?

Title: Re: TE0890 Clock Input from Oscillator
Post by: JH on June 24, 2020, 07:05:20 AM

Hi,
add set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets netname] constrain.
--> Vivado should also make this suggestion in the messages window.

br
John

Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: flakmasta on June 24, 2020, 12:12:07 AM