Print Page - Xilinx Artix-7 XC7A200T-2FBG484I ADC functionality

Title: Xilinx Artix-7 XC7A200T-2FBG484I ADC functionality
Post by: Varun on April 30, 2018, 02:33:43 PM

Hi,

I am using Xilinx Artix-7 XC7A200T-2FBG484I(TE0712) board and TE0701 carrier board for my project.

As per the Xilinx document, for 7 series board they have two sets of Analog inputs:
1) VP and VN
2) VAUXP[15:0] and VAUXN[15:0]

When see the schematic of TE0712 board, VP and VN are exposed but VAUXP/VAUXN are not exposed.

We would like to VAUXP/VAUXN are connected to any I/O pins or those pins are not used in this board?

Regards,
Varun

Title: Re: Xilinx Artix-7 XC7A200T-2FBG484I ADC functionality
Post by: JH on April 30, 2018, 02:59:38 PM

Hi,
AUX Pins are labled as '_AD*' see:

https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf (https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf)
page 16-table 1.1

Some are accessible (Bank 15 on schematics) some not (Bank 35 --> DDR) for example see page 5, 7:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/REV02/Documents/SCH-TE0712-02-100-1I.PDF

You must test, if you can use only some of them on the Xilinx IP:

https://www.xilinx.com/support/documentation/ip_documentation/xadc_wiz/v3_0/pg091-xadc-wiz.pdf

br
John

Title: Re: Xilinx Artix-7 XC7A200T-2FBG484I ADC functionality
Post by: Varun on April 30, 2018, 03:24:34 PM

Hi John,

Thanks for the quick information.

Regards,
Varun

Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: Varun on April 30, 2018, 02:33:43 PM