Hi,
I have a problem to get the hyperram working correctly I use the cypress IP Core with 50mhz clock
I write 0x11223344 and read back 0x10223244
Anyone have a idea what i do wrong?
Thanks,
codi78
there is probably some finetuning required, the cypress IP is for ASIC mainly for FPGA there need count the FPGA I/O delays etc
thanks for your reply i will take a look in to that
We have made "PHY" testing only to read back the ROM ID Code, so we made some finetuning to get the base PHY timings correct, but this was done 100% as project from scratch, not from cypress IP, and we did not use 4 phases at all the way cypress IP suggests the IO timing.
HI
I am working on new TE0725 board , I want to configure hyper-RAM with Microblaze ....I know how to use DDR with Microblaze ... but in this TE0725 board nothing I am getting can any one please help me out. or give any example code you find , please provide link.
mailID - shubham.dwivedi@eiwave.com
Quote from: codi78 on February 08, 2017, 02:27:59 PM
I have a problem to get the hyperram working correctly I use the cypress IP Core with 50mhz clock ... Thanks, codi78
Hi Codi78. I can assist you to get a working HyperRAM memory controller solution. Please contact me directly on: chip.dev@yahoo.com. Cheers.
Quote from: eiwave on March 14, 2018, 06:39:38 AM
HI
I am working on new TE0725 board , I want to configure hyper-RAM with Microblaze ....I know how to use DDR with Microblaze ... but in this TE0725 board nothing I am getting can any one please help me out. or give any example code you find , please provide link.
mailID - shubham.dwivedi@eiwave.com
Hi just a quick note that https://synaptic-labs.force.com/s/ip-hbmc (https://synaptic-labs.force.com/s/ip-hbmc) HyperRAM IP core work well on TE0725, we have tested it. More info to follow soon.
Hi, a have also the 0725 with the hyperram .
Is there any update on this??
I have tried the cypress ip core and it need a lot of work to get it working.
Best Regards
Lasse
Hello, i am currently writing my own HyperRAM Controller for a selfmade Board. In order to test my controller in Vivado Simulation i need the HyperRAM "Chip" as (V)HDL. Does anyone have such an HDL?
Yes, Cypress offers the Download https://www.cypress.com/verilog/s27kl0641-verilog , but it needs VITAL 2000 Librarys. I got some VITAL Librarys from GHDL and importet these in Vivado, but the Project is still missing some Librarys.
So ... i would also be very greatful if someone tells me how to use VITAL 2000 with Vivado simulator.
Thank You!
Quote from: -gb- on February 06, 2020, 09:24:27 PM
Hello, i am currently writing my own HyperRAM Controller for a selfmade Board.
Synaptic Labs offers a free trial (no registration required, 10 minute run-time) of our HyperBus Memory Controller IP for Xilinx: https://synaptic-labs.force.com/s/free-trials-xilinx-fpga (https://synaptic-labs.force.com/s/free-trials-xilinx-fpga).
This IP supports HyperRAM and HyperFlash and has been extensively tested on a wide range of Trenz HyperRAM enabled Xilinx boards.
SLL also offers a free trial (no registration required, 10 minute run-time) of the same IP for a broad range of Intel FPGA devices: https://synaptic-labs.force.com/s/ip-hbmc?tabset-98c60=2 (https://synaptic-labs.force.com/s/ip-hbmc?tabset-98c60=2).
This IP has also been tested on Trenz HyperRAM enabled Intel FPGA boards.
SLL is actively exploring how we can improve support very low volume customers and Hobbyists.
Please send all enquiries to b.gittins@synaptic-labs.com.
Benjamin Gittins, CTO, Synaptic Laboratories Limited
Hello again, i wrote my own little HyperBus Controller. For the Simulation i used the verilog models i found on the Internet.
The zip file contains the wohole project for simulation. Simulate till 663 us.
You may use the code for your projects and you may adapt, copy, ... feel free!
Edit:
Is this a very bad joke? I cannot upload .vhdl in an forum related to fpga? But zip - a fileformat which can contain virusses - is perfecly OK with you? Really?
So the i renamed the .vhdl to .vhdl.txt - which is very bad because windows per default hides the endling so you see .vhdl but cannot use it because it is a .txt hidden from you.
At least you also forbid .v so it is equally painful for both.
Hi,
sorry for it, it was an oversight. vhd, vhdl and v should work now.
Best Regards,
Thorsten Trenz