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#41
Trenz Electronic FPGA Modules / Re: Flash QSPI TE0820 with 202...
Last post by JH - February 14, 2024, 09:12:18 AMHi,
different can be QSPI is with our without design...or like I say some other issue.
Try to change boot mode to JTAG only, if it works, than it's problem with AMD software only.
Let me know if you need help again.
br
John
different can be QSPI is with our without design...or like I say some other issue.
Try to change boot mode to JTAG only, if it works, than it's problem with AMD software only.
Let me know if you need help again.
br
John
#42
Trenz Electronic FPGA Modules / Re: Flash QSPI TE0820 with 202...
Last post by Adrien - February 12, 2024, 03:42:56 PMI happened to have other products from Trenz. I just tried with TE0820-05-4AE81MA REV5 and a carrier TE0703-05 this time and it works, first try. I am still using Xilinx 2022.2 tools on Windows 10 and the switch on the carrier is configured the same. I just did the same, launch _create_win_setup.cmd, create binaries, create zynqmp_fsbl (TE modified) with sw_libs/ and prebuilt .xsa file. I just don't know. If I have time I will test on the previous setup.
#43
Trenz Electronic FPGA Modules / Re: Flash QSPI TE0820 with 202...
Last post by JH - February 12, 2024, 08:00:49 AMHi,
here are some information about this topic:
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=105689937
At the end you should change boot mode to JTAG for flash programming, if you want to use newer Vivado version.Workaround with special FSBL seems to work less and less with each newer Version...
So simple install oder Vivado Labtools version (best was 17.2 as long as it now the device and the flash) and try again.
Or change boot mode to JTAG (there are different ways possible, depending on your carrier and CPLD Firmware). ways depends on CPLD Firmware, see CPLD Firmwar update and Variants:
https://wiki.trenz-electronic.de/display/PD/TE0820+CPLD+Firmware
Of course, it is also possible that the FSBL has a problem and simply crashes (FSBL does not match variant or module defective or simply a power problem). But I can't say that with your information yet. You could first boot from the SD card and see if that works.
br
John
here are some information about this topic:
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=105689937
At the end you should change boot mode to JTAG for flash programming, if you want to use newer Vivado version.Workaround with special FSBL seems to work less and less with each newer Version...
So simple install oder Vivado Labtools version (best was 17.2 as long as it now the device and the flash) and try again.
Or change boot mode to JTAG (there are different ways possible, depending on your carrier and CPLD Firmware). ways depends on CPLD Firmware, see CPLD Firmwar update and Variants:
https://wiki.trenz-electronic.de/display/PD/TE0820+CPLD+Firmware
Of course, it is also possible that the FSBL has a problem and simply crashes (FSBL does not match variant or module defective or simply a power problem). But I can't say that with your information yet. You could first boot from the SD card and see if that works.
br
John
#44
Trenz Electronic FPGA Modules / Flash QSPI TE0820 with 2022.2 ...
Last post by Adrien - February 09, 2024, 04:41:23 PMI am trying to flash the QSPI of a TE0820-04-4DE21FA with a carrier board TE0703-06 with 2022.2 Xilinx tools.
So I did _create_win_setup.cmd, generate binaries and tried to flash _binaries_TE0820-04-4DE21FA\boot_linux with _binaries_TE0820-04-4DE21FA\res_elf\fsbl.elf or SDMODE\fsbl_flash.elf with the command `C:\Xilinx\Vitis\2023.2\bin\program_flash -f BOOT.bin -fsbl fsbl_flash.elf -flash_type qspi-x8-dual_parallel -url tcp:localhost:3121` with the Switch S2-1 & S2-2 & S2-3 On and S2-4 Off but nothing works and I have the following:
>> ===== mrd->addr=0xFF5E0204, data=0x00000222 =====
>> BOOT_MODE REG = 0x0222
>> WARNING: [Xicom 50-100] The current boot mode is QSPI32.
>> Flash programming is not supported with the selected boot mode.If flash programming fails, configure device for JTAG boot mode and try again.
>> Downloading FSBL...
>> Running FSBL...
>> ===== mrd->addr=0xFFD80044, data=0x00000000 =====
>> ===== mrd->addr=0xFFD80044, data=0x00000000 =====
>> ...
>> ERROR: [Xicom 50-331] Timed out while waiting for FSBL to complete.
>> Problem in Initializing Hardware
>> Flash programming initialization failed.
I know about using the fsbl_flash to get around this QSPI mode to use JTAG instead but I just don't get how I am supposed to find/create/use it.
There is no zynqmp_fsbl_flash in sw_libs/sw_app/ in zip 2022.2. I tried to generate zynqmp_fsbl with prebuilt 4ev_1e_2gb, use a fsbl_flash from previous version...
So I did _create_win_setup.cmd, generate binaries and tried to flash _binaries_TE0820-04-4DE21FA\boot_linux with _binaries_TE0820-04-4DE21FA\res_elf\fsbl.elf or SDMODE\fsbl_flash.elf with the command `C:\Xilinx\Vitis\2023.2\bin\program_flash -f BOOT.bin -fsbl fsbl_flash.elf -flash_type qspi-x8-dual_parallel -url tcp:localhost:3121` with the Switch S2-1 & S2-2 & S2-3 On and S2-4 Off but nothing works and I have the following:
>> ===== mrd->addr=0xFF5E0204, data=0x00000222 =====
>> BOOT_MODE REG = 0x0222
>> WARNING: [Xicom 50-100] The current boot mode is QSPI32.
>> Flash programming is not supported with the selected boot mode.If flash programming fails, configure device for JTAG boot mode and try again.
>> Downloading FSBL...
>> Running FSBL...
>> ===== mrd->addr=0xFFD80044, data=0x00000000 =====
>> ===== mrd->addr=0xFFD80044, data=0x00000000 =====
>> ...
>> ERROR: [Xicom 50-331] Timed out while waiting for FSBL to complete.
>> Problem in Initializing Hardware
>> Flash programming initialization failed.
I know about using the fsbl_flash to get around this QSPI mode to use JTAG instead but I just don't get how I am supposed to find/create/use it.
There is no zynqmp_fsbl_flash in sw_libs/sw_app/ in zip 2022.2. I tried to generate zynqmp_fsbl with prebuilt 4ev_1e_2gb, use a fsbl_flash from previous version...
#45
Trenz Electronic FPGA Modules / Re: use prebuilt files
Last post by Lilly_567 - January 30, 2024, 12:39:04 PMHi,
thank you a lot for your help. The problem was the inverted switch.
I am sorry it took so long for me to reply.
Again, thank you so much. I am so happy that I can finally start to work.
Kind regards,
Lilly
thank you a lot for your help. The problem was the inverted switch.
I am sorry it took so long for me to reply.
Again, thank you so much. I am so happy that I can finally start to work.
Kind regards,
Lilly
#46
UltraScale / Re: TE0808/TE0803 Linux - Unab...
Last post by logmaster - January 26, 2024, 01:13:02 PMHi everyone,
I found a working solution here:
https://support.xilinx.com/s/question/0D54U00005wQoYhSAK/have-error-with-cat-prociomem-in-linux-board-zynqmp?language=en_US
Basically, this error appears when the PS is configured with 64bit DRAM bus. Setting it to 32bit resolved the issue.
Is there an explanation why this happens? Is it a known problem?
Thank you!
I found a working solution here:
https://support.xilinx.com/s/question/0D54U00005wQoYhSAK/have-error-with-cat-prociomem-in-linux-board-zynqmp?language=en_US
Basically, this error appears when the PS is configured with 64bit DRAM bus. Setting it to 32bit resolved the issue.
Is there an explanation why this happens? Is it a known problem?
Thank you!
#47
UltraScale / Re: xczu4ev_0 PL Power Status ...
Last post by logmaster - January 26, 2024, 01:09:00 PMHello everyone,
for whom ever who is facing issue at the moment, I found an explanation that describes why this warning appears. On my side this warning appears only if the image has secure boot features enabled. That means encryption and/or authentication. When those features are disabled, the Vivado Hardware Manager and ILAs work fine.
If you would like to test your hardware design with the Hardware Manager and use secure boot features, make sure to first do your testing on a non secure image and afterwards enable security.
Thank you!
for whom ever who is facing issue at the moment, I found an explanation that describes why this warning appears. On my side this warning appears only if the image has secure boot features enabled. That means encryption and/or authentication. When those features are disabled, the Vivado Hardware Manager and ILAs work fine.
If you would like to test your hardware design with the Hardware Manager and use secure boot features, make sure to first do your testing on a non secure image and afterwards enable security.
Thank you!
#48
UltraScale / TE0808/TE0803 Linux - Unable t...
Last post by logmaster - January 17, 2024, 03:30:52 PMHello Everyone,
I am currently facing a problem with Vivado 2019.2, Petalinux 2019.2 and TE0808/TE0803 on the TEBF0808 carrier board:
I was able to successfully export my custom design (.xsa) from Vivado and build the petalinux project I got from the StarterKit. The image that was created is booting properly. The issue occurs when I try to either execute an application which maps a physical address space to virtual memory using mmap, or when I try to run
it both cases the kernel crashes and I get an error message saying:
I can understand that maybe the custom app that I am using to access memory is faulty, but why running cat /proc/iomem is leading to the same issue?
Have some of you encountered something similar? I have not used any custom files, like the FSBL, from the StarterKit, only the custom petalinux project.
Any tips will be appreciated!
Thank you!
I am currently facing a problem with Vivado 2019.2, Petalinux 2019.2 and TE0808/TE0803 on the TEBF0808 carrier board:
I was able to successfully export my custom design (.xsa) from Vivado and build the petalinux project I got from the StarterKit. The image that was created is booting properly. The issue occurs when I try to either execute an application which maps a physical address space to virtual memory using mmap, or when I try to run
Code Select
cat /proc/iomemit both cases the kernel crashes and I get an error message saying:
Code Select
Unable to handle paging request at virtual address ...I can understand that maybe the custom app that I am using to access memory is faulty, but why running cat /proc/iomem is leading to the same issue?
Have some of you encountered something similar? I have not used any custom files, like the FSBL, from the StarterKit, only the custom petalinux project.
Any tips will be appreciated!
Thank you!
#49
Trenz Electronic FPGA Modules / Re: TE0820 as PS-PCIe Endpoint...
Last post by pema - January 16, 2024, 02:10:34 PMWell, this doesn't look like a very approached subject.
Perhaps because EP in this SOC is not as much used as RC. Also perhaps because PCI Express CEM Specification defines a 100-msec rule from the de-assertion time of the PERST# (slot reset) to the time that a PCI Express root complex (host) is allowed to probe the connected downstream endpoint.
At the time being Xilinx/AMD does not provide the device driver for PCIe EP controller. Just for Host/RC.
This could perhaps be modified to EP as well and make it usable in the PCI EP Framework.
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/pci/controller/pcie-xilinx-nwl.c
Perhaps because EP in this SOC is not as much used as RC. Also perhaps because PCI Express CEM Specification defines a 100-msec rule from the de-assertion time of the PERST# (slot reset) to the time that a PCI Express root complex (host) is allowed to probe the connected downstream endpoint.
At the time being Xilinx/AMD does not provide the device driver for PCIe EP controller. Just for Host/RC.
This could perhaps be modified to EP as well and make it usable in the PCI EP Framework.
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/pci/controller/pcie-xilinx-nwl.c
#50
Trenz Electronic FPGA Modules / Re: TE0820 as PS-PCIe Endpoint...
Last post by pema - January 10, 2024, 11:23:14 AMHi there again,
well I am now back to the ps-pcie EP issue. I remembered I disabled the NWL bridge controller drivers(since in this was being said to work only for the Root complex mode).
The problem is if I disable the NWL PCIe Core drivers the device is no longer found on (therefor no probe takes place). If I enable them and I try to write to the BARs I get :
In Baremetal I was able to perform a basic example and get the PCIe EP to work based on the https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/pciepsu/examples/xpciepsu_ep_enable_example.c
I realize that this is perhaps a question that should be directed to AMD/Xilinx rather than Trenz, but perhaps you have already used the TR0820 +TEF1002 as EP with Linux. Or perhaps you already have a demo for the TEF1002 carrier board?
I would appreciate any help.
Best
well I am now back to the ps-pcie EP issue. I remembered I disabled the NWL bridge controller drivers(since in this was being said to work only for the Root complex mode).
The problem is if I disable the NWL PCIe Core drivers the device is no longer found on (therefor no probe takes place). If I enable them and I try to write to the BARs I get :
Code Select
nwl-pcie fd0e0000.pcie: Unsupported request Detected
In Baremetal I was able to perform a basic example and get the PCIe EP to work based on the https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/pciepsu/examples/xpciepsu_ep_enable_example.c
I realize that this is perhaps a question that should be directed to AMD/Xilinx rather than Trenz, but perhaps you have already used the TR0820 +TEF1002 as EP with Linux. Or perhaps you already have a demo for the TEF1002 carrier board?
I would appreciate any help.
Best