Hi,
I am relatively new to using FPGA modules and have a potentially basic question regarding the typical power consumption of FPGA boards in an idle state. I am using the TE0890 and the idle power consumption seems to be around 100mA when supplying 5V to the board. This is when the board has not yet been programmed, so everything should be completely idle. This seems quite high as someone who has previously worked with low-power microcontrollers.
After programming the board's flash memory, the current draw on the 5V line drops to approximately 65mA. Following a power cycle, the chip then reads the flash ROM and starts up. Whilst reading the ROM the current is roughly 100mA, this then jumps to roughly 130mA when running the 'Hello World' reference design.
Is there any way to reduce the idle power consumption of this board? I am planning to use this board for a battery powered application so any reduction in power consumption is helpful. Is there a reason that the current drops by 35mA after the ROM has been programmed - is something (i.e., flash memory, FPGA core itself) being switched off?
Thanks in advance for any help.
Hello cjc220,
The TE0890 contains no control signals that could disable unused power supplies or delay FPGA configuration.
In the old datasheet of HyperRam U2 there is a note that in Power On Reset mode it consume about 50mA. I would recommend to pull the signal CS0 high to turn off the IC.
https://www.issi.com/WW/pdf/66-67WVH8M8ALL-BLL.pdf
Best regards,
Vadim
I also have the same problem. I found the answer the best until I read your article. I tried pulling the CS0 signal high to turn off the IC and it worked fine. Thank.