Author Topic: DDR issue on TE715  (Read 63 times)

ks

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DDR issue on TE715
« on: June 10, 2021, 11:17:35 AM »
I have a TE0715-04-12S-1C that I am trying to bring up, but I wasn't able to boot the pre-built or self-built binaries from the test board project. Booting from SD and QSPI both failed due to CRC errors on loading the bitstream. In the Xilinx forums it was suggested that it could be a DDR issue. I built and ran the memory test program from Vitis, and indeed it failed on DDR checks. Here's the output:

Code: [Select]
--Starting Memory Test Application--
NOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated
Testing memory region: ps7_ddr_0
    Memory Controller: ps7_ddr_0
         Base Address: 0x100000
                 Size: 0x1FF00000 bytes
          32-bit test: FAILED!
          16-bit test: FAILED!
           8-bit test: FAILED!
Testing memory region: ps7_ram_1
    Memory Controller: ps7_ram_1
         Base Address: 0xFFFF0000
                 Size: 0xFE00 bytes
          32-bit test: PASSED!
          16-bit test: PASSED!
           8-bit test: PASSED!
--Memory Test Application Complete--

For completion, this is the output of the FSBL with enabled debugging output and checksums:

Code: [Select]
Xilinx First Stage Boot Loader
Release 2019.2  Jun 10 2021-11:07:55
Devcfg driver initialized
Silicon Version 3.1
Watchdog driver initialized
Boot mode is SD
SD: rc= 0
SD Init Done
Flash Base Address: 0xE0100000
Reboot status register: 0x60500000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 3
Partition Number: 1
Header Dump
Image Word Len: 0x00013A08
Data Word Len: 0x00013A08
Partition Word Len:0x00013A08
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000075D0
Partition Attr: 0x00001020
Partition Checksum Offset: 0x0003E2E0
Section Count: 0x00000001
Checksum: 0xFFF7E6C6
Bitstream
In FsblHookBeforeBitstreamDload function
Actual checksum
0x3A 0x5B 0x28 0xDD 0x19 0x39 0x2F 0x38 0xAC 0x4B 0x98 0xD 0x52 0x8A 0x6E 0xE4
Calculated checksum
0x93 0x9D 0x37 0xED 0x49 0x58 0x27 0x2 0xC8 0x63 0xBC 0x5B 0x9 0x7E 0x87 0xA
Error: Partition DataChecksum 0x3A!= 0x93
PARTITION_CHECKSUM_FAIL
FSBL Status = 0xA010

This Boot Mode Doesn't Support Fallback
In FsblHookFallback function

What could be the cause? I already tried setting the DDR timings manually in the Vivado project, according to the memory part data sheet, but haven't yet found a working configuration.

The carrier board is a custom one, but I don't see how this could affect DDR.

JH

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Re: DDR issue on TE715
« Reply #1 on: June 11, 2021, 06:25:15 AM »
Hi,
Quote
I have a TE0715-04-12S-1C that I am trying to bring up, but I wasn't able to boot the pre-built or self-built binaries from the test board project.
Did you use newest version of the prebuilt binaries?
Did you use correct Boot.bin for  TE0715-04-12S-1C assembly variant? Did you use ".prebuilt/boot_images/04_12s_1c_1gb/hello_te0715/Boot.bin ?
If not can you try out this and boot from SD?
Do you have one of our carrier on place?

Quote
The carrier board is a custom one, but I don't see how this could affect DDR.
Normally it doesn't effect ddr, but maybe you has some power problem. However, it is rather unlikely at this point.

br
John

ks

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Re: DDR issue on TE715
« Reply #2 on: June 11, 2021, 03:06:18 PM »
Hi John,

thanks for your fast reply. We did test the two latest versions (2019.2 and 2020.2) and both produced the same result. I did try the prebuilt/boot_images/04_12s_1c_1gb/hello_te0715 as well as the binaries copied by _create_linux_setup.sh, and wasn't able to boot any of them. The provided binaries only produce two lines of text output, as the FSBL doesn't have debugging enabled. Over JTAG however, we can see that the CRC error bit is set.

We did measure the voltage rails of the carrier board and there is no measurable noise there (fluctuations are within the resolution limit of the oscilloscope). Currently there isn't much hardware running on the carrier board and we even desoldered some of the non-crictical components. We used the TE0706 schematics as orientation for our board design. The only peculiar thing I find is that we don't have a JB3, as we didn't need these IOs.

Unfortunately we don't have a different carrier board for testing. We have ordered some TE0820 modules, but as you know they are currently out of stock (we bought the TE0715 so we could test our carrier board until the TE0820 modules can be shipped).

Regards,
Konstantin

JH

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Re: DDR issue on TE715
« Reply #3 on: June 11, 2021, 03:29:57 PM »
Hi,
can you write to "support@trenz-electronic.de" and send me the schematics of your carrier? In case this is problematical, B2B connect part is the most important part for me, if this is OK for you. Can you also send me the serial number of your TE0715. it's the small number with QR Code on the module.

Quote
The provided binaries only produce two lines of text output, as the FSBL doesn't have debugging enabled
can you send me a screenshot of these outputs?

br
John