Author Topic: TE0820 Power consumption reduction  (Read 65 times)

engkan2kit

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TE0820 Power consumption reduction
« on: June 04, 2021, 10:12:11 AM »
Hi,

I'm using the TE0820 4CG 2gb version. I currently using linux with 1 core. Most of the BSP from the reference design is intact. I'm getting around 750mA (3.3V VIN) of current. All available PL IOs are LVCMOS 1.8 where 1.8V VCCIO is supplied also by the 3.3V via a 1.8V regulator
Here's my setup:
1. using the si5334 to generate 100Mhz for the USB3.0
2. not using the SD card and eMMC. But eMMC is enabled.
3. not using Ethernet.
4. using the qSPI for storage (initramfs)
5. dropbear is running as well as rndis and the webdfu.
6. ram speed and cpu speed are the same from board_test design file.

Is there a way to further lower the consumption? Do you have a data on actual consumption of the clock circuit referenced by the USB3.0? Because I'm planning to replace this with a lower power 100Mhz XO in my custom board and just remove the inductors of the VCC of the XO and si5334 in the module.

Thank you.

JH

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Re: TE0820 Power consumption reduction
« Reply #1 on: June 08, 2021, 07:10:06 AM »
Hi,
zynqmp has a lot of mechanism to modify power consumption. Default a lot things are activated. Reduce fore example DDR bus size(use only half of DDR) and DDR speed and check PMU firmware. Disable also all interfaces which are not use (regenerate FSBL, and linux files).
Sorry I can't help much more on this topic.

Here is a little bit documentation, which maybe also helps:
https://www.xilinx.com/support/documentation/white_papers/wp482-zu-pwr-perf.pdf
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
--> see PMU part
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841813/Zynq%2BUltraScale%2BMPSoC%2BPower%2BManagement

br
John