Recent Posts

1

UltraScale / Re: TE0841 with AFE7422 Evaluation Module

« Last post by JH on October 21, 2021, 06:37:17 AM »

Hi,

I got the info from your reply that both Evaluation boards [ AFE7422 & TE0841 ] shall work by purchasing additional JESD204b IP core from Xilinx ?

You need also a carrier which forward correct Modules IOs to SMA Connectors (it looks like AFE7422  use SMA for JESD). And yes, theoretical it should work. But you must setup everything correctly by yourself and it also depends on the final lane rate and length and quality of your transmission lane.

is there any help/guidance available on this forum by integrating JESD204b IP core in the BSP provided by Trenz along with TE0841 EVM ?

I think not much. I've less experience with JESD IP from Xilinx.

br
John

2

Trenz Electronic FPGA Modules / Re: Requirements for xil_printf on CPU1

« Last post by PitG on October 20, 2021, 11:03:39 AM »

Hi,

   Yes, you're right.
   
   Although I am familiar with microcontrollers and SoC, Zynq 7000 is quite complicated and a lot of things are new for me and difficult to understand.
   Nevertheless I will try to go forward ( that's my hobby).
   TE0722 maybe is not the easiest board to learn, but it has lots of resources, is small and cheap, and that's its advantage.
 
Thank You for help,
PitG.

3

UltraScale / Re: TE0841 with AFE7422 Evaluation Module

« Last post by FRK on October 20, 2021, 06:52:20 AM »

Thank you for your response .

I got the info from your reply that both Evaluation boards [ AFE7422 & TE0841 ] shall work by purchasing additional JESD204b IP core from Xilinx ? . is there any help/guidance available on this forum by integrating JESD204b IP core in the BSP provided by Trenz along with TE0841 EVM ?

warm regards

4

UltraScale / Re: TE0841 with AFE7422 Evaluation Module

« Last post by JH on October 19, 2021, 03:47:50 PM »

Hi,
no we haven't any carrier where you can use TE0841  together with AFE7422  EVM.

AFE7422  used JESD204b standard over high speed lanes. TE0841  has also high speed lanes (GTH), but for JESD204, you need additional IP from Xilinx, which is not free available.

We haven't any carrier which forward these IOs to SMA connectors like on the AFE7422  EVM board.

On option is your design your own one. We offer the altium projects of the most of our carriers on the download area of the carrier, this will help to speed up carrier designing.

br
John

5

Trenz Electronic FPGA Modules / Re: Requirements for xil_printf on CPU1

« Last post by JH on October 19, 2021, 03:41:46 PM »

"Did you use the same FSBL when you generate the Boot.bin, like you has used for debugging? "   - this question is too complicated for me, so I can't answer this. Probably not. I test my project by writing it into flash first.

You wrote you xilprintf works when you start it with SDK (I assume you use the debugger which loads your FSBL with your the code directly into the OCM and starts it.). You can also generate a boot.bin with SDK. and I mean if you has use the same fsbl software project like you hast start it from SDK over debugger? Not that you have another FSBL. 

Maybe you should also ask on Xilinx forum, I can't help much more on this topic. This is internal Xilinx stuff.

PS: TE0722 is not the easiest board to learn how Xilinx Zynqand Xilinx software works.
br
John

6

Trenz Electronic FPGA Modules / Re: Requirements for xil_printf on CPU1

« Last post by PitG on October 19, 2021, 10:34:03 AM »

Hello,

  I had a problem with power supply long time ago, so now I use separate supply and problem with power supply is solved. I'm not an expert in SoC ZYNQ. It's only my hobby, so my project is not as good as it should be. I'm experimenting with it to achieve run both CPUs. I've started application in CPU1 by simply copying partition CPU1ap.elf from Flash into last region OCM, setting jump to the beginning of this region and waking up by sev instruction. I've spotted that "outputbyte(char c)" function, which is inside xil_printf works correctly, so I deduce that problem should be inside xil_printf function before "outputbyte(char c)" is called.

"Did you use the same FSBL when you generate the Boot.bin, like you has used for debugging? "   - this question is too complicated for me, so I can't answer this. Probably not. I test my project by writing it into flash first.

All the best,
PitG
 

7

UltraScale / TE0841 with AFE7422 Evaluation Module

« Last post by FRK on October 18, 2021, 08:37:25 AM »

Dear All,

I want to use TE0841 EVM with Texas Instrument AFE7422 EVM . We have background experience working on other vendor module but this will be our first time to use Trenz EVM  board.

My question is there any RFSoC or SoM available combining TE0841 and AFE7422 ? and what are other accessories that needs to be order with above mentioned hardware to work together ?

warm regards 

8

Trenz Electronic FPGA Modules / Re: Vivado synth error due to two IP cores having submodules with the same name

« Last post by JH on October 18, 2021, 07:26:03 AM »

Hi,
I would suggest you use Xilinx IP Wizard and you select new AXI4-Periherial. In this case you has standard defines to use it in Vitis and petalinux:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1118-vivado-creating-packaging-custom-ip.pdf
page 30ff

it looks like 20.1 has a bug, so use other Vivado version:
https://support.xilinx.com/s/article/75655?language=en_US

Xilinx information about special features are mostly rare, often it helps when you check Xilinx IPs itself (C:\Xilinx\Vivado\<Vivado Version>\data\ip) to get such information.

br
John

9

Trenz Electronic FPGA Modules / Re: Requirements for xil_printf on CPU1

« Last post by JH on October 18, 2021, 07:17:13 AM »

Hi,
as I know there should be no special requirements.

When I debug CPU1 application then xil_printf function works OK and CPU1 not abort.

hm, strange.
Which external power supply did you use? Some current limit?  It is unlikely, but maybe you are somewhere close to the limit and when the second CPU starting faster, voltage drops down shortly and system stops?

Did you use the same FSBL when you generate the Boot.bin, like you has used for debugging?

Can you clean the project and generate the Boot.bin again, maybe something was not generated correctly.


br
John

10

Trenz Electronic FPGA Modules / Requirements for xil_printf on CPU1

« Last post by PitG on October 16, 2021, 10:22:44 AM »

Hello,

   I've started application program on CPU1 TE0722 board. It works (controls green LED on board) but only without xil_printf function. When I add xil_printf function, CPU1 aborts and LED is not controlled even before xil_printf function in CPU1. What are requirements for xil_printf function on CPU1 ? CPU0 is inside FsblHandoff function and works OK. When I debug CPU1 application then xil_printf function works OK and CPU1 not abort.

All the best,
PitG