Recent Posts

1

Trenz Electronic FPGA Modules / TE0820 Flash eMMC over JTAG

« Last post by pema on Today at 04:37:46 PM »

Hi there,
I would like to flash the eMMC flash on the TE0820 over JTAG. I already modified my kit so that the boot_mode pins can be changed to JTAG and eMMC bootmodes. Currently is booting over JTAG.
Correct me if I am wrong but isn't it the eMMC @0xFF17 0000 ? and SD card @ 0xFF16 0000 ?
Because when it enters u-boot it selects memory at ff160000 for emmc flashing

Code: [Select]

sdhci@ff160000: 0
ZynqMP> mmc dev 0 0
switch to partitions #0, OK

The process gets stuck at 0%

Code: [Select]

ZynqMP> 0%...Any ideas what might be ? I would appreciate any help.

Output from program_flash (hw_server running on a parallel terminal)

Code: [Select]

$ program_flash -f BOOT.BIN -fsbl zynqmp_fsbl.elf -flash_type emmc -emmc_partition_size large -blank_check -verify -target_id 3 -frequency 15000000 -url tcp:localhost:3121

****** Xilinx Program Flash
****** Program Flash v (64-bit)
  **** SW Build (by xbuild) on 2022-10-05-18:51:07
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.


Connected to hw_server @ tcp:localhost:3121
Supported Frequency list
125000  250000  500000  1000000  2000000  3000000  3750000  5000000  6000000  7500000  10000000  15000000  30000000 

Retrieving Flash info...

Initialization done
Using default mini u-boot image file - ./55457_zynqmp_emmc.bin.50Mhz
===== mrd->addr=0xFF5E0204, data=0x00000000 =====
BOOT_MODE REG = 0x0000
Downloading FSBL...
Running FSBL...
===== mrd->addr=0xFFD80044, data=0x00000000 =====
===== mrd->addr=0xFFD80044, data=0x00000000 =====
===== mrd->addr=0xFFD80044, data=0x00000000 =====
===== mrd->addr=0xFFD80044, data=0x00000002 =====
===== mrd->addr=0xFFD80044, data=0x00000003 =====
Finished running FSBL.
===== mwr->addr=0xFF18031C, data=0x64406440 =====
===== mwr->addr=0xFF180314, data=0x01150000 =====
===== mwr->addr=0xFF180318, data=0x00450043 =====
NOTICE:  ATF running on XCZU3EG/silicon v4/RTL5.1 at 0xfffea000
NOTICE:  BL31: Secure code at 0x60000000
NOTICE:  BL31: Non secure code at 0x10000
NOTICE:  BL31: v1.3(release):
NOTICE:  BL31: Built : 10:38:42, Feb  1 2017


U-Boot 2022.01-00146-g0526f91 (Jul 27 2022 - 03:13:13 -0600)

Model: ZynqMP MINI EMMC0
Board: Xilinx ZynqMP
DRAM:  512 MiB
EL Level: EL2
MMC:   sdhci@ff160000: 0
Loading Environment from <NULL>... OK
In:    dcc
Out:   dcc
Err:   dcc
ZynqMP> mmc list
sdhci@ff160000: 0
ZynqMP> mmc dev 0 0
switch to partitions #0, OK
mmc0(part 0) is current device
ZynqMP> mmc list
sdhci@ff160000: 0 (eMMC)
ZynqMP> mmc dev 0 0
switch to partitions #0, OK
mmc0(part 0) is current device
ZynqMP> Performing Erase Operation...
mmc dev 0 0
switch to partitions #0, OK
mmc0(part 0) is current device
ZynqMP> 0%...

Here the output from the serial console

Code: [Select]

TE0820 TE_XFsbl_HookPsuInit_Custom
Configure PLL: SI5338
Si5338 Init Registers Write.
Si5338 Init Complete
PLL Status Register 218:0x8                                       
USB Reset Complete
ETH Reset Complete

------------------------------------------------------------------------------

--------------------------------------------------------------------------------
Xilinx Zynq MP First Stage ot Loader (TE modified)
Release 2021.2   May 26 2023  -  150:09
Device Name: XCZU3CG
MultiBootOffset: 0x0
Reset Mode : System Reset
Platform: Silicon (4.0), Cluster ID 0x800000
Running on A53-0 (64-bit) Processor, Device Name: XCZU3C
--------------------------------------------------------------------------------
TE0820 TE_XFsbl_BoardInit_Custom

------------------------------------------------------------------------------
Processor Initialization Done
================= In Ste 2 ============
In JTAG Boot Mode
================= In Ste 4 ============
PMU-FW is not running, certain applications may not be supported.
Protection configuration appliedExit from FSBL


2

MAX1000 community projects / Re: SD Ram Controller for MAX100

« Last post by philippe69 on Today at 12:24:09 PM »

Hello Everybody,
I asked to Winbond to obtain their SDRAM driver. Find it enclosed.
But, with my level, I couldn't get it to work.

maybe Trenz could help us by providing us with a driver and a design using it ;-))

3

Trenz Electronic FPGA Modules / Re: TE0790 under virtual box Ubuntu Guest

« Last post by pema on Today at 09:58:26 AM »

Hi John,
many thanks for your reply .
I am posting here a solution that worked for me... for posterity  :-)
All you need is either Xilinx Vivado/Vitis or petalinux in my case.

Code: [Select]

$ cd ~/petalinux/2022.2/tools/xsct/data/xicom/cable_drivers/lin64/install_script/
$ sudo ./install_drivers
$ sudo ./setup_pcusb
$ sudo su -
$ cd /etc/udev/rules.d
$ sed -i -e 's/MODE=/MODE:=/g' 52-xilinx*.rules
$ exit
$ sudo udevadm control --reload
#optional
$ echo "alias xsct="$HOME"/./petalinux/2022.2/tools/xsct/bin/xsct" >> ~/.bashrc
$ echo "alias xsct="$HOME"/./petalinux/2022.2/tools/xsct/bin/xsdb" >> ~/.bashrc

Test it.

Code: [Select]

$ xsct
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.
                                                                                                                                             
****** Xilinx Software Commandline Tool (XSCT) v2022.2.0
  **** SW Build 0 on 2022-10-05-18:51:07
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.


WARNING: sdtgen package cannot be loaded. System Device tree commands will not                                                               
be available
xsct% connect                                                                                                                                 
tcfchan#0
xsct% targets                                                                                                                                 
  1  PS TAP
     2  PMU
     3  PL
  4  PSU
     5  RPU (Reset)
        6  Cortex-R5 #0 (RPU Reset)
        7  Cortex-R5 #1 (RPU Reset)
     8  APU (L2 Cache Reset)
        9  Cortex-A53 #0 (APU Reset)
       10  Cortex-A53 #1 (APU Reset)



4

Trenz Electronic FPGA Modules / Re: TE0790 under virtual box Ubuntu Guest

« Last post by JH on Today at 06:22:26 AM »

Hi,
as I know this can happens and I didn't have a solution.
Here they recommend to install cable drivers again:
https://support.xilinx.com/s/question/0D52E00006hphZuSAI/jtag-not-working-on-virtual-box-ubuntu-1604?language=en_US

I use AMD(Xilinx) tools with WSL:
https://wiki.trenz-electronic.de/display/PD/AMD+Tools+and+Win10+WSL
In this case there is there is a trick, which maybe also works on virtual box(but I didn't expect it).
Start HW_Manager.exe on WinOS (C:\Xilinx\Vivado\<vivado version>\bin\unwrapped\win64.o\hw_server.exe). In case the server is running, Vivado from WSL automatically connect to the HW server and JTAG is availabe.
br
John

5

UltraScale / Re: Upgrade Toolchain 2019.2 to 2021.2: Petalinux Build Errors

« Last post by davidmarco on May 29, 2023, 09:27:21 AM »

Hi,
can you try out our 21.2 template with our prebuilt xsa files, this should works:
https://wiki.trenz-electronic.de/display/PD/TE0808+StarterKit/drift hunters
Template project is in:
https://wiki.trenz-electronic.de/display/PD/TE0808+StarterKit#TE0808StarterKit-DesignSources
copy xsa from prebuilt folder to the petalinux folder and start with point 3 "petalinux-config --get-hw-description"
https://wiki.trenz-electronic.de/display/PD/PetaLinux+KICKstart#PetaLinuxKICKstart-CreatingaProjectfromVivadoProject

in case this doesn't work, check your build environment.
https://wiki.trenz-electronic.de/display/PD/PetaLinux+KICKstart#PetaLinuxKICKstart-PetaLinuxInstallation

I use Ubuntu 20.4 on WSL which was working fine.
br
John

Thanks for this post!

6

Trenz Electronic FPGA Modules / Re: TEM0001-01A - UART transmission issues with the "test board" reference design

« Last post by pmjobin on May 28, 2023, 11:17:22 PM »

Hello Kilian,

Thank you for your help. I followed all the instructions from the lab guide as you suggested and the serial terminal is now displaying correctly formatted text again. This validates that my hardware & software setup is functioning correctly.

Concerning the reference design, on thing I noticed will browsing the source code of the helloWorld SoftConsole project is that the baudrate is set to a non-standard value of 161280 (see attachment). I tried changing it back to 115200 and rebuilding the project but it did not fix the serial transmission corruption issue I was experiencing.

Thanks again,
P-M

7

Trenz Electronic FPGA Modules / Re: TEM0001-01A - UART transmission issues with the "test board" reference design

« Last post by Kilian Jahn on May 26, 2023, 01:46:04 PM »

Hello pmjobin ,
i am the one who build the design for this board. I downloaded the online zip file like you did and I check on my board the design via FlashProExpress programming, via Libero programming with and without recompiling and soft core updates. I could not reproduce your error.

Your Uart settings are right , but your error description brings to my mind that the Uart Terminal and the board are out of sync . Can you try a different Uart Terminal ? I tried SmartTTY and Softconsole , both worked fine on my board .

There are older Demo projects available . They are based on a different Hardware and Software Design .
Via " Download  ->  lab_guides  ->  archive " you will find everything that you need .
The guide "SMF2000_Cortex_M3_PWM_lab_guide_Lib2021d3_SC2021d3_v1.5.pdf "
explains it in great detail . Most interesting is the demo "RTC_time application" .

Regards Kilian

8

Trenz Electronic FPGA Modules / TE0790 under virtual box Ubuntu Guest

« Last post by pema on May 26, 2023, 11:17:19 AM »

Hi there,
this is most likely a issue caused by VirtualBox rather than the TE0790. But perhaps someone is experiencing the same issue and knows a work around.
Since I perform most of the development under a virtual machine, I would also like to have access to the JTAG probe under Linux virtual machine.

The problem:
When I connect the TE0790 to the VM I am able to connect through the xsdb or xsct but not able to list the targets( bellow you find the output).

Code: [Select]

ubuntu@ubuntu-VirtualBox:~$ lsusb
Bus 001 Device 003: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
Bus 001 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
ubuntu@ubuntu-VirtualBox:~$ xsdb
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.
                                                                                                                                             
****** System Debugger (XSDB) v2023.1
  **** Build date : May  7 2023-15:13:35
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.


xsdb% connect                                                                                                                                 
attempting to launch hw_server
                                                                                                                                             
****** Xilinx hw_server v2023.1
  **** Build date : May  7 2023 at 15:13:34
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application

INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121

tcfchan#0
xsdb% targets                                                                                                                                 
xsdb%      

Under Windows Host this does not happens:

Code: [Select]

C:\Xilinx\Vitis\2022.2\bin
λ .\xsct

****** Xilinx Software Commandline Tool (XSCT) v2022.2.0
  **** SW Build 0 on 2022-10-13-12:09:39
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.


xsct% connect
tcfchan#0
xsct% targets
  1  PS TAP
     2  PMU
     3  PL
  4  PSU
     5  RPU (Reset)
        6  Cortex-R5 #0 (RPU Reset)
        7  Cortex-R5 #1 (RPU Reset)
     8  APU (L2 Cache Reset)
        9  Cortex-A53 #0 (APU Reset)
       10  Cortex-A53 #1 (APU Reset)
xsct%
Anyone having the same issue? I can of course be always switching between VM and Host  to developt and flash or debug. But like I said is quite tedius to switch between both.

Greetings

9

Trenz Electronic FPGA Modules / Re: TE0820 Flash eMMC and/or QSPI over JTAG

« Last post by pema on May 24, 2023, 08:26:54 AM »

Many thanks! I will give it a try.

10

Trenz Electronic FPGA Modules / TEM0001-01A - UART transmission issues with the "test board" reference design

« Last post by pmjobin on May 23, 2023, 07:41:16 PM »

Hello,

I bought a SMF2000 FPGA module in early 2019 and just got around to trying it out. As a first step (after installing Libero 21.2 and before overwriting the factory image), I opened a serial terminal on the COM port (115200 bauds 8N1) that appeared after I connected the board to my PC in order to validate that the serial connection was working as intended, which it did. The message that was displayed in the terminal was a large "MICROSEMI" title followed by "Hello PolarFire! This is SmartFusion2.". I'm pointing this out in case it helps identifying the factory image that was present on my board.

Next, I programmed the "TEM0001_test-board_Libero-2021.2" reference design provided on your website using the FlashPro Express method outlined in the wiki. In other words, I did not rebuild the design, I merely took the image straight out of the archive and programmed it as is on the board. Since then, all the text that appears in the serial terminal is garbled. I tried playing with the COM port settings to no avail. I believe the image was programmed correctly because the led patterns operate as expected. I also managed to connect to the JTAG port and step through the code of the "HelloWorld" application in SoftConsole.

Before diving further, I would prefer to get the serial communication up and running with the reference design. Any suggestion as to what steps I should take next?

Regards,
P-M