Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: markiz on March 29, 2022, 09:37:35 AM

Title: TE0712: LVDS signals on +3.3V bank
Post by: markiz on March 29, 2022, 09:37:35 AM
Hello,

I am working on a design of a carrier board for TE0712, I am trying to use some clock capable pins for driving a number of ADCs with LVDS interface. I am able to use the banks with 2.5V supply, but the question is are the LVDS signals also available on the bank14 which is supplied from the module with fixed 3.3V supply. The ADCs have the 2.5V supply for the LVDS, I was not able to find the specifications for the LVDS signals on the 3.3V supplied bank if this is even possible.
Title: Re: TE0712: LVDS signals on +3.3V bank
Post by: JH on March 30, 2022, 06:45:22 AM
Hi,
Output is not possible but maybe input (This is probably the case with you :-)), Xilinx has some AR about this topic:
https://support.xilinx.com/s/article/43989?language=en_US
br
John
Title: Re: TE0712: LVDS signals on +3.3V bank
Post by: Antti Lukats on May 16, 2022, 08:56:33 AM
Hello,

I am working on a design of a carrier board for TE0712, I am trying to use some clock capable pins for driving a number of ADCs with LVDS interface. I am able to use the banks with 2.5V supply, but the question is are the LVDS signals also available on the bank14 which is supplied from the module with fixed 3.3V supply. The ADCs have the 2.5V supply for the LVDS, I was not able to find the specifications for the LVDS signals on the 3.3V supplied bank if this is even possible.

LVDS output buffers get disabled when VCCIO is detected above 2.65V so LVDS output is not possible, input is possible without onchip termination.