Hi,
We bought a te808 kit with the XCZU15EG-1FFVC900E FPGA. I have tested the module with the starter kit in Vivado 2018.2 and everything was fine. However, when we add our IP module, the tool is not able to synthesize. In spite of this fact, I synthesized a similar design without the Trenz IPs in Vivado 2016.4 and the design synthesize without any problem. Therefore, it is a problem of the tool, However there are not any starter kit for Vivado 2016.4. We wanted to know if there would be the possibility to have an example block design in Vivado 2016.4, in order to synthesize our design and create a petalinux image. We really need to deploy our design in that version.
Thanks in advance
Hi,
this UltraScale+Zynq was not available in 16.4:
- https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug973-vivado-release-notes-install-license.pdf
br
John