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1
Trenz Electronic FPGA Modules / Re: TE0712 oscillators drift
« Last post by ame on August 05, 2022, 12:21:45 PM »
Hi,
I would recommend to generate Xilinx IBERT IP for different line rates and check eye diagrams, to see quality of your channels.
Maybe a little bit slower line rate works. You can also try to adjust setup a little with IBERT to get better channel quality.Properties can be changed on Auroa IP later also.
br
John
I will try it.

Thank you for your help.
Regards
2
Trenz Electronic FPGA Modules / Re: TE0712 oscillators drift
« Last post by JH on August 05, 2022, 06:51:28 AM »
Hi,
I would recommend to generate Xilinx IBERT IP for different line rates and check eye diagrams, to see quality of your channels.
Maybe a little bit slower line rate works. You can also try to adjust setup a little with IBERT to get better channel quality.Properties can be changed on Auroa IP later also.
br
John
3
Trenz Electronic FPGA Modules / Re: TE0712 oscillators drift
« Last post by ame on August 04, 2022, 02:43:35 PM »
Hi,
fmeter of the reference design is not accurate enough.
It simple compare calculate clk with 2 counter (one with known and one with unkown clk). from relationship you get the result on vivado HW Manager.
It's only used to see that a clock is there with appr. frequency which you expect.


You say "I'm using two TE0712 with SI5338A feeded by (SiT8008BI) to initiate Aurora link it runs smoothly."
You use default MGT_CLK0_P/N in this case? SI5338 use default 125 MHz clk on this pin. Where everything works.

So when you change reference input in your aurora IP from MGT0 to MGT1, you must also change reference clk from 125MHz to 100MHz
--> the result are different lanerate. In case the line rate does not match, you get never a link.
--> I think this is maybe your problem when I see you picture (but when I see your final table, you had change something did you changed si5338 configuration?).

Instead of Aurora, instantiate Xilinx ibert test. Configure input clks and lane rate and export IP example. Compile this example project and start ibert on both modules, where you has this 100MHz from your PC.

Check at first if the MGT PLLs locks (if they don't lock, than you has a problem with your reference clk). If they locks, check line rate and create eye diagram of the lanes.

br
John

Thanks for your reply.
Yes I configure SI5338A  from TE0712 reference design to 100MHz. The problem is from PCIE gen2 allow +-300ppm jitter  and Aurora link support only +-100ppm jitter. More most low-cost pcie-RP use SpreadSpectrumClk so I cannot feed Aurora-link from standard pcie-RP clk.

Thanks again for your help.

Alexandre.M
4
Trenz Electronic FPGA Modules / Re: how to share a vitis project with 2 PCs
« Last post by JH on August 04, 2022, 11:50:23 AM »
Hello,
that's more a question for Xilinx forum.
Only post I found is(but not exactly what you search for): https://support.xilinx.com/s/question/0D52E00006hpOLwSAM/how-to-share-source-files-in-vitis?language=en_US


Maybe use virtual drive, so that both PCs has same paths...
Or add only source code folder to SVN or GIT --> synchronise code there and every PC has his own project....

We itself generate template for final application, which can be load as local repository into vitis (see auch reference designs and https://wiki.trenz-electronic.de/display/PD/Vitis).  --> but this is only good for final code, not for sharing development state...

br
John
5
Trenz Electronic FPGA Modules / Re: TE0712 oscillators drift
« Last post by JH on August 03, 2022, 04:27:00 PM »
Hi,
fmeter of the reference design is not accurate enough.
It simple compare calculate clk with 2 counter (one with known and one with unkown clk). from relationship you get the result on vivado HW Manager.
It's only used to see that a clock is there with appr. frequency which you expect.


You say "I'm using two TE0712 with SI5338A feeded by (SiT8008BI) to initiate Aurora link it runs smoothly."
You use default MGT_CLK0_P/N in this case? SI5338 use default 125 MHz clk on this pin. Where everything works.

So when you change reference input in your aurora IP from MGT0 to MGT1, you must also change reference clk from 125MHz to 100MHz
--> the result are different lanerate. In case the line rate does not match, you get never a link.
--> I think this is maybe your problem when I see you picture (but when I see your final table, you had change something did you changed si5338 configuration?).

Instead of Aurora, instantiate Xilinx ibert test. Configure input clks and lane rate and export IP example. Compile this example project and start ibert on both modules, where you has this 100MHz from your PC.

Check at first if the MGT PLLs locks (if they don't lock, than you has a problem with your reference clk). If they locks, check line rate and create eye diagram of the lanes.

br
John
6
Trenz Electronic FPGA Modules / how to share a vitis project with 2 PCs
« Last post by rschaefer on July 29, 2022, 01:38:05 PM »
Hello,

I have used the share function for version control which was fine.
Now a college has to work with me on the same project but the platform and appl. system project uses (local) absolute paths (e.g. path to sysroot).

Could anybody plaese give me a hint for a good practise or a tutorial to share vitis projects between 2 colleges or PCs?
7
Trenz Electronic FPGA Modules / TE0712 oscillators drift
« Last post by ame on July 29, 2022, 12:42:41 PM »
Hello,

I'm using two TE0712 with SI5338A feeded by (SiT8008BI) to initiate Aurora link it runs smoothly.
Then from only one of TE0712 I replace SI5338A (MGT0) by PCIE (MGT1) clock from PC. And the link do never UP with exactly the same design.

So I use labtool FrequencyMeter to mesure my PCIE clock with SI5338A  as reference clock.
Mesured PCIE clock is 99.76MHZ . So it's -2400ppm drift from 100MHz , almost 10 times more than the 300ppm specified by the PCIE spec. The pcie have also strong rms jitter.
I mesure the clock from another PC and the mesure is 99.77MHz. So SI5338A ref clock looks imprecise.

I program SI5338A to 99.76MHz to board 1, and try to sync the Aurora link with board 2 (feeded by pcie  clock) and it still do not works.

My question is, do the SI5338A feeded by (SiT8008BI +-50ppm after 1years)  is enough precise and stable to synch with a PCIE clock?
From the SI5338A datasheet yes but it seems to not be the case.
Could the clocks of the two PCs have shifted by aging? (More than 5 years PC)

Regards

PS: Aurora test summary:

-----------------------------------------------------------------------------
Aurora   |  Source CLK  MB   |  MainBoard      | ITF (always Si5338)
    OK    |   Si5338               |  125MHz          | 125MHz
    OK    |   Si5338               |  99.79MHz       | 99.79MHz
    OK    |   Si5338               |  100MHz          | 100MHz   
    KO    |   Si5338               |  99.76MHz       | 99.99MHz
    KO    |   PCIE                  |  99.79MHZ       | 100MHz
    KO    |   PCIE                  |  99.76MHZ       | 99.76MHz

8
Trenz Electronic FPGA Modules / Re: Problem with programming TE0745 QSPI Flash
« Last post by JH on July 25, 2022, 07:02:17 AM »
Hi,

problem is, that it seems that Xilinx change something on the JTAG programming procedure and this does not longer work together with devices where boot mode is not jtag only.
FSBL Flash simple change boot mode for software to JTAG only an disabled DDR (this is normally not need):
https://wiki.trenz-electronic.de/display/PD/TE0745+Test+Board#TE0745TestBoard-zynq_fsbl_flash.1
--> Search for "TE Mod" on the source code to see our changes (test_board\sw_lib\sw_apps\zynq_fsbl_flash\src).
it's more or less what Xilinx has recommended here: https://support.xilinx.com/s/article/70548?language=en_US

This changes works up to Vivado 19.2. For 2020.2 you must also change boot mode to a interface where the devices doesn't find an valid image, otherwise Vivado starts fsbl from this image instead of the selected one from vivado. With 21.2 this kind of workaround does not longer works.  We start now to change our CPLD Firmware step by step to allow customer easier to select jtag only boot mode(either change definition of some of the controller signals to get more boot modes selectable or offer different kind of CPLD firmware --> replace SD boot or QSPI boot mode with JTAG only boot mode as option firmare).
 
I has wrote done, different behaviour and possible solutions for different vivado versions:
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=105689937

br
John
9
Trenz Electronic FPGA Modules / Problem with programming TE0745 QSPI Flash
« Last post by Daniel_Kan on July 22, 2022, 07:25:37 PM »
Hi,
I am using a TE0745 module with the self designed carrier board. The module has OK performance while RAM programming, But It is not possible to program QSPI flash and It doesn't recognize QSPI memory on module and returns JEDEC error code as programming process log. I tried by vivado19.1+SDK and vivado19.2+vitis. Also I changed boot mode to JTAG_MODE in main.c file in src of fsbl project. I have also tried with fsbl_flash.elf downloaded from ref design of trenz and it recognized QSPI memory, confirmed there doesn't exist any hardware problem. Whould you please guide me how to solve this problem? Is it necessary to edit ps7_init or other files?
Thanks in advance
10
Trenz Electronic FPGA Modules / Re: Vitis SCU_TE0712 application
« Last post by ame on July 22, 2022, 05:53:02 PM »
Quote
My guess to your problem is, that while you want to run your hello world application, the FPGA is still being configured. Could you try programming the FPGA with the bitstream in vivado manually and then run your application from Vitis like descried in this tutorial -> Figure 12 + 13

https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=157219241

It should run your app without reconfiguring the system.

Thank you very much. App works great now :).
I remember now it's a classic trap with ┬ÁBlaze but it's been more than five years I didn't use ┬ÁBlaze.

Quote
In the reference design CLK0 is 100MHz.
Yes but I need 100MHz to feed MGT_CLK to run aurora link.

Quote
The program that configures the SI5338 exactly is scu_te0712.elf. Source files are in ...\test_board\sw_lib\sw_apps\scu_te0712\src.
If you rebuild this app(at the moment manually) you can replace the old scu_te0712.elf in ...\test_board\firmware\microblaze_mcs_0 with the new one(keep the same name) and generate bitstream again.
It will be linked to the microblaze_mcs which configures the Si5338 at startup.
I did as you said and it run smooth.

Thank you again for your help.
It saved me a lot of time.

Regards.
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