Hello,
I am working on a project where previously NIOS II was used and NIOS II Code was loaded through external SDRAM on the Cyclone IV E (EP4CE40F23C8) FPGA. It works fine without any issue.
Now as per the requirement of the project, NIOS II needs to replaced with NIOSV processor. If I run the NIOSV through On-Chip-Ram, the code executes well as expected. But when I try to run the NIOSV code through external SDRAM, ELF gets loaded successfully but the code does not executes as expected.
I have already make sure to set the reset vector in NIOSV to the SDRAM Controller IP. The BSP settings are also made accordingly.
Following are my questions regarding the issue:
- 1 : Is NIOSV processor applicable to run through external SDRAM ?
- 2 : If yes to Q.1, then what is the procedure I need to follow in order to run the NIOSV processor through external SDRAM.
FYI:
- Quartus Version used : Quartus Prime Standard 22.1.1
- RiscFree IDE for creating software project.
- FPGA : Cyclone IV E (EP4CE40F23C8)
- External SDRAM Part No on the Cyclone IV FPGA : W9816G6IH ( WinBond )
Any help regarding this issue would be appreciated. Thanks !!
Regards,
Himanshu
Hello,
I am writing this to follow up on the issue that I have mentioned. Any feedback would be appreciated.
Thanks!!
Regards,
Himanshu
Hello,
i see you have already posted this question on the intel forum,
regarding your question you should be much better advised there than here.
best regards
Waldi
Hi himanshu,
we now have a reference design available online for our TEI0003 CYC1000 board with Nios V/m running through an external SDRAM (Winbond W9864G6JT-6).
- Wiki description: https://wiki.trenz-electronic.de/display/PD/TEI0003+Test+Board (https://wiki.trenz-electronic.de/display/PD/TEI0003+Test+Board)
- Download link: https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/2.5x6.15/TEI0003/Reference_Design/22.1/test_board (https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/2.5x6.15/TEI0003/Reference_Design/22.1/test_board)
The IP Core used is an AXI4 sdram controller from Github. The source code was only slightly adapted for Quartus.
- Source code on github: https://github.com/ultraembedded/core_sdram_axi4 (https://github.com/ultraembedded/core_sdram_axi4)
You can simply copy the IP Core and try it out on your board.
br
Thomas