My setup is simple on the 701:
VDMA -> AXI to Video (with timing control) -> Video to HDMI IP (from Trenz) -> AD chipset.
Rock solid at 1080P @ 50 Hz (timing clock / IP clock set to 123.75.
But - dancing pixels at edges of high contrast lines when I up the clock to 148.5mhz (1080p@60)
I don't see how any of the code violates max timing of the Artix-7 module. (speed grade 2) and the AD chipset can handle up to 220mhz. Also not a cable or display issue.
AXI running at 180mhz, DDR3 is 32bit and has 256 bit AXI at 100mhz. There should be no bandwidth issues.. but I'm open to questions here.
Ideas?
Hi!
Are you see any timing problems in the report?
Also which clock is showing your clocking wizard block in the "Actual" column?
BR
Oleksandr Kiyenko
The design has timing violations in DVI2RGB on the input side decoding TMDS at 800 Mhz+ .. but I see no timing violations on the output. I see no input artifacts and I see the same output issue with input on and off..
Yes, I get a clean 148.5mhz out of the clocking wiz (200mhz in from DDR3). Output is not central to my design (only for debugging) and I'm ok with 50hz frames for now.. just unexpected..
The only think I can think of is some timing issue in the conversion from 148.5mhz to DDR at half the rate. I'm using your IP which I took from your zynq reference design. I made one change.. I skip swapping Red and Green (or whatever you do for Linux FB compatibility). I can take another look if that might change timing..