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#91

Trenz Electronic FPGA Modules / Re: Inter-FPGA-Communication: ...

Last post by Trensica - October 25, 2023, 06:28:16 AM

This configuration is capable of achieving a practical data rate close to 10Mbps from the master device to the clients. It is mentioned that this data rate exceeds the previously used BMC (b1b2) encoding commonly used in S/PDIF in S/PDIF (Sony/Philips Digital Interface) audio connections.

In the context of professional systems, it is suggested that a Low Voltage Differential Signaling (LVDS) implementation using 4 wires would be the optimal choice. LVDS is a signaling method that provides high-speed and noise-immune data transmission. It typically uses a differential pair of wires to transmit data and a separate pair for the complementary signal, resulting in a total of four wires.

#92

Trenz Electronic FPGA Modules / Petalinux-package, unsupported...

Last post by embedded.kyle - October 24, 2023, 10:52:00 PM

I have used the PetaLinux tools to add an application to the system image and built it. I am now attempting to add it into the bitstream file so that I can program it into my FPGA.

I am using a Trenz electronic TE0841 with an XCKU040. I have not made any changes to the reference design code yet so I'm just using the prebuilt bitstream file provided by Trenz. I have only added a small application in PetaLinux.

I have been following UG1144 as closely as I can.

First I created a project with

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petalinux-create --type project --template microblaze --name <PROJECT_NAME>

Then I imported the HW configuration supplied by Trenz Electronic in the prebuilt directory of their reference design

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petalinux-config --get-hw-description <PATH-TO_XSA>

I found that petalinux-package would fail when I got to that step due to the partition layout. So while in the configuration menu, I modified the partition table to fit the various components based on the error output of petalinux-package. Then I save the configuration.

I created and enabled an application and then added my code to it

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petalinux-create -t apps --name <APP-NAME> --enable

Then I built the system image

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petalinux-build

That populated the images/linux directory with the various build outputs.

Finally, I tried to add the system image to the bitstream supplied by Trenz Electronic with the petalinux-package command

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petalinux-package --boot --flash-size 64 --flash-intf SPIx4 --fpga /home/kyle/petalinux/bsps/test_board_02_40_1i_2gb.bit --u-boot --kernel

And this is the output I get

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kyle@DESKTOP-U0P8IUP:~/petalinux/projects/plnx-rad-test$ petalinux-package --boot --flash-size 64 --flash-intf SPIx4 --fpga /home/kyle/petalinux/bsps/test_board_02_40_1i_2gb.bit --u-boot --kernel
[INFO] Sourcing buildtools
WARNING: Auto detecting MMI file with XSA
INFO: Creating download.bit...
INFO: Fpga bitstream: /home/kyle/petalinux/bsps/test_board_02_40_1i_2gb.bit
INFO: Fpga bitstream MMI file: /tmp/tmp.a5s1iUmgk8/test_board_02_40_1i_2gb.mmi
INFO: Fsbl file: /home/kyle/petalinux/projects/plnx-rad-test/images/linux/fs-boot.elf
INFO: Output download.bit: /home/kyle/petalinux/projects/plnx-rad-test/images/linux/download.bit
INFO: Getting system flash information...
WARNING: Failed to detect SPI width from bitstream.
WARNING: Using default one: SPIx1.
WARNING: User specified Flash interface SPIx4 is different to the auto detected one SPIx1. Will use the user specified one.
INFO: Add bitstream "/home/kyle/petalinux/projects/plnx-rad-test/images/linux/download.bit" to 0.
INFO: Add datafile "/home/kyle/petalinux/projects/plnx-rad-test/images/linux/u-boot-s.bin" to 0x640000.
INFO: Add datafile "/home/kyle/petalinux/projects/plnx-rad-test/images/linux/image.ub" to 0x720000.
INFO: Add datafile "/home/kyle/petalinux/projects/plnx-rad-test/images/linux/boot.scr" to 0x1f00000.
INFO: Generating MCS file...
ERROR: [Bitstream 40-51] Unsupported part xcku040-sfva784-1-i in bitfile /home/kyle/petalinux/projects/plnx-rad-test/images/linux/download.bit.
ERROR: [Writecfgmem 68-7] Could not load bitfile /home/kyle/petalinux/projects/plnx-rad-test/images/linux/download.bit.
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Fri Oct 20 08:29:00 2023
# Process ID: 107470
# Current directory: /home/kyle/petalinux/projects/plnx-rad-test/build/package-boot
# Command line: vivado -log /home/kyle/petalinux/projects/plnx-rad-test/build/package-boot//cfgmem.log -jou /home/kyle/petalinux/projects/plnx-rad-test/build/package-boot//cfgmem.jou -mode batch -s /home/kyle/petalinux/projects/plnx-rad-test/build/package-boot//write_cfgmem_hsm.tcl
# Log file: /home/kyle/petalinux/projects/plnx-rad-test/build/package-boot//cfgmem.log
# Journal file: /home/kyle/petalinux/projects/plnx-rad-test/build/package-boot//cfgmem.jou
# Running On: DESKTOP-U0P8IUP, OS: Linux, CPU Frequency: 2687.999 MHz, CPU Physical cores: 10, Host memory: 16634 MB
#-----------------------------------------------------------
source /home/kyle/petalinux/projects/plnx-rad-test/build/package-boot//write_cfgmem_hsm.tcl
# write_cfgmem -force -format MCS -size 64 -interface SPIx4 -loadbit " up 0 /home/kyle/petalinux/projects/plnx-rad-test/images/linux/download.bit" -loaddata " up 0x640000 /home/kyle/petalinux/projects/plnx-rad-test/images/linux/u-boot-s.bin up 0x720000 /home/kyle/petalinux/projects/plnx-rad-test/images/linux/image.ub up 0x1f00000 /home/kyle/petalinux/projects/plnx-rad-test/images/linux/boot.scr" /home/kyle/petalinux/projects/plnx-rad-test/images/linux/boot.mcs
Command: write_cfgmem -force -format MCS -size 64 -interface SPIx4 -loadbit { up 0 /home/kyle/petalinux/projects/plnx-rad-test/images/linux/download.bit} -loaddata { up 0x640000 /home/kyle/petalinux/projects/plnx-rad-test/images/linux/u-boot-s.bin up 0x720000 /home/kyle/petalinux/projects/plnx-rad-test/images/linux/image.ub up 0x1f00000 /home/kyle/petalinux/projects/plnx-rad-test/images/linux/boot.scr} /home/kyle/petalinux/projects/plnx-rad-test/images/linux/boot.mcs
Creating config memory files...
Creating bitstream load up from address 0x00000000
Loading bitfile /home/kyle/petalinux/projects/plnx-rad-test/images/linux/download.bit
ERROR: [Bitstream 40-51] Unsupported part xcku040-sfva784-1-i in bitfile /home/kyle/petalinux/projects/plnx-rad-test/images/linux/download.bit.
ERROR: [Writecfgmem 68-7] Could not load bitfile /home/kyle/petalinux/projects/plnx-rad-test/images/linux/download.bit.
0 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.
write_cfgmem failed
ERROR: [Common 17-39] 'write_cfgmem' failed due to earlier errors.

    while executing
"write_cfgmem -force -format MCS -size 64 -interface SPIx4 -loadbit " up 0 /home/kyle/petalinux/projects/plnx-rad-test/images/linux/download.bit" -load..."
    (file "/home/kyle/petalinux/projects/plnx-rad-test/build/package-boot//write_cfgmem_hsm.tcl" line 1)
INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 08:29:06 2023...
ERROR: Failed to run Vivado write_cfgmem command.

What does this error mean? How can I debug this further?

Unsupported part xcku040-sfva784-1-i in bitfile

I have followed the same procedure using the 02_35_2i_2gb prebuilt images and the petalinux-package command will then complete without an error. I do not have a KU035 board to test if it successfully inserted my petalinux build and application into the bitstream. But in any case, I do not receive the error that I do when trying to use the KU040.

#93

UltraScale / Re: TE0802 Data Rate

Last post by faly477a - October 23, 2023, 03:47:05 PM

https://shop.trenz-electronic.de/de/TE0802-02-1BEV2-A-MPSoC-Development-Board-mit-AMD-Zynq-UltraScale-ZU1EG-und-1-GB-LPDDR4


Here is the link for the product.

#94

UltraScale / TE0802 Data Rate

Last post by faly477a - October 23, 2023, 03:44:30 PM

Hello Guys, my supervisor asked me to test the date rate at communication between TE0802. Is there a specific Software or tool for this test? Or should I write a test programm by myself ?


Thank you  

#95

Open source IP / Re: Labtools fmeter

Last post by ame - October 19, 2023, 11:23:38 AM

Hello,
Yes, that is possible. The Fmeter is a simple frequency counter that simply calculates the ratio between known and unknown frequencies.
br
John

Great  . Thank you for your quick reply.

#96

Open source IP / Re: Labtools fmeter

Last post by JH - October 19, 2023, 06:45:56 AM

Hello,
Yes, that is possible. The Fmeter is a simple frequency counter that simply calculates the ratio between known and unknown frequencies.
br
John

#97

Open source IP / Labtools fmeter

Last post by ame - October 18, 2023, 06:18:21 PM

Hello,

I would like to know about the Trenz IP "Labtools fmeter" IP Licence terms.
There is no Licence terms in the source files.
Is it possible to use IP in a commercial project without violating any license terms?

Regards

#98

CYC1000 community projects / Re: Utility to flash FPGA

Last post by lauryfriese - October 18, 2023, 11:13:04 AM

This is so helpful, thanks for the idea.

#99

UltraScale / Re: TE0807 clock wizard lock f...

Last post by JH - October 11, 2023, 06:57:13 AM

Hi,
I must have overlooked your answer. Sorry.
Voltages are actually measured before delivery. It is strange that it was missing. But I'm glad you were able to solve the problem.
br
John

#100

UltraScale / Re: TE0807 clock wizard lock f...

Last post by cs_wiz - October 09, 2023, 04:50:14 AM

Hi,

Yes I am programming the Si5345 in my baremetal code and the power line is also enabled.
As I mentioned in my reply post, this was due to a hardware fault. I managed to get it working after replacing the resistors.

Cheers.