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1
Open source hardware / Re: DIPFORTy1 questions
« Last post by dbutter on August 18, 2017, 08:08:04 PM »
Hello,

I initially tested by just placing the module on a breadboard and applying power, and I observed that it got hot. This used whatever was in the flash when shipped, which may be nothing. I then loaded the reference design, and again it gets hot.

Currently I have the module plugged into my custom carrier board and I have placed a small heatsink on the zynq. This keeps the temp to around 65-70C.

I would like to know if this is expected for the DIPFORTy or if I may have a bad set of modules?

Do you have a DIPFORTy module (with the Z7010 part) you can check and confirm whether or not you see similar temperatures?

Thanks for your help!
--
Regards, Devin
2
Open source hardware / Re: DIPFORTy1 questions
« Last post by JH on August 18, 2017, 11:59:56 AM »
Hello,

80C is very hot.  Temperature depends on design and environment, 60 or 70°C or little bit more should be ok for moderate design. Module is very small so it's hard to spread the head.

Did you use default design or your own? Did you put it on another board or standalone usage? So you can dissipate the head a little bit.

br
John
3
Trenz Electronic FPGA Modules / Re: TE0728 booting from sd card
« Last post by JH on August 18, 2017, 09:17:49 AM »
4
Trenz Electronic FPGA Modules / Re: TE0728 booting from sd card
« Last post by aashwin on August 18, 2017, 09:08:44 AM »
The latest available for the board which is 2016.2
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Trenz Electronic FPGA Modules / Re: TE0728 booting from sd card
« Last post by JH on August 18, 2017, 08:21:28 AM »
Hi,

this depends on Xilinx SW and drivers. So it's not included to TRM.

which Vivado/Petalinux version did you use at the moment?

Add following to the device tree:
Code: [Select]
/* ETH PHY */
&gem0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {

            device_type = "ethernet-phy";
            reg = <0>;
        };
    };
};



br
John
6
Trenz Electronic FPGA Modules / Re: TE0728 booting from sd card
« Last post by aashwin on August 18, 2017, 03:32:55 AM »
I've had the chance to work on this again. I have a somewhat functional petalinux running on sd. Could you please steps on enabling Ethernet on the device. I couldn't make too much sense from the information provided on the TRM.


Thanks.
7
Open source hardware / Re: DIPFORTy1 questions
« Last post by dbutter on August 17, 2017, 10:06:43 PM »
Hello,

Sorry for the slow reply, I was pulled off this project for a while...back to it again.

>> 2: Can you measure the temperature? You can use XADC on Xilinx Vivado HW-Manager.

Yes when I look at the XADC temp sensor it shows that a running DIPFORTy commercial temp is running at ~80C !!

I see this on two boards I received from Digikey. Both are handled at an ESD safe workstation.

So what does this mean? What temperatures do you see when you check XADC in HW manager?

Other than temp issues, the board seem to be fully functional. Thanks.
--
Regards, Devin
8
Trenz Electronic FPGA Modules / Re: No GTX REFCLK3 on TE041, hardware issue?
« Last post by JH on August 17, 2017, 12:10:30 PM »
Hi,

Si5338 CLK2(for MGTCLK3) is default not configured. See:

CLK0 IO Standard LVDS
CLK1 und CLK2 for MGT Ref did not need this property.

PLL can be reconfigured over I2C. At the moment we have no example online. We will add one on the 17.1 reference design (working in process, not available at the moment).
We do the same with TE0841. You can check this example.
Procedure:
1. Add MPU with GPIO to I2C
2. Generate Firmware with I2C configuration (see TE0841)

To get correct register file for SI5338 configuration, use SI5338 ClockBuilder Desktop from Silicon Laboratories.


br
John
9
Trenz Electronic FPGA Modules / No GTX REFCLK3 on TE041, hardware issue?
« Last post by xetnik on August 16, 2017, 04:23:56 PM »
Hi everyone,

I am using the TE0741-160-2CF together with the TEBA0841. I am able to get a signal from the clock sources GTX REFCLK1 and Bank 14 input clock but not GTX REFCLK3 (naming from the TE041 TRM page 9). I have enabled the PLL reference via the CLK_EN Pin C26 on the FPGA.

I measured the clock signals on the U2 Si5338 Chip and also there I only get the clock signals from CLK0A/CLK0B and CLK1A/CLK1B (naming from the Si5338 Datasheet). Is there something I am missing, do I have to activate the MGTCLK3 in a special way or is this a hardware issue?

Also, where do I find the right IOSTANDARD properties for these clock pins (LVDS_25/LVCMOS33)?.

Thank you in advance and best regards,
xetnik
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Trenz Electronic FPGA Modules / Re: TE0720 1.8V DCDC failure
« Last post by Thorsten Trenz on August 15, 2017, 02:11:57 PM »
Hi,
you can sent the shematic of your setup to support at trenz- electronic.de
We will review it, and may point out possible reasons.
In general, there is no problem with 1.8V powersupply.

Best Regards,
Thorsten Trenz
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