Hello. I'm trying to boot Te0713 form flash. I'm working with Vivado 2017.4 and I'm using TE0703 as base board. I generated mcs file with the command
write_cfgmem -force -format mcs -interface SPIx1 -size 32 -loadbit "up 0x0 ".bit location" " -file mynewmcs.mcs
And after this the file mynewmcs.mcs is generated.
Then I selected in vivado the S25FL256Sxxxxxx0 flash and I flashed it without error messages. On TE0703 switch S4 is in OFF position and in this way the fpga could boot from flash but nothing happen. Where is the mistake? Thanks for the help!
Hi,
you used SPIx1 --> slower.
Did you set bitfile compression as parameter(also possible as xdc)?
S2-4 Boot Mode is no matter on pure FPGA. This is used only for Zynq.
Maybe you must wait a little bit.
Programming was successfully? Did you enable validation?
br
John
Hi. Thank you for the quick reply! I also tried setting SPIx4 writing in .xdc
set_property COMPATIBLE_CONFIG_MODES {{Master SPI x4}} [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
And then I generated the mcs through the command
write_cfgmem -force -format mcs -interface SPIx4 -size 32 -loadbit "up 0x0 ".bit location" " -file mynewmcs.mcs
Is this correct?
However validation I remember it was enabled (in this moment I have not the FPGA in my hand). I didn't enable bitfile compression. Is it mandatory? Yes programming was successfully. Thank you very much for the help!
Quote
I didn't enable bitfile compression. Is it mandatory?
Bigger bitfile -->longer time for programming.
I've generated scripts so i didn't need to know what I must put into console, but it seems to be OK. My scripts use:
- write_cfgmem -force -format mcs -interface SPIx4 -size 32 -loadbit {up 0x0 <bitfile path>} -file <mcs file>
You can also use Vivado GUI Interface instead of TCL, newer Version has GUI Option for MCS Generation with Vivado. But It's the same.
You should add this to you xdc:
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
SPI Buswidth property is needed on bitfile generation, before you can generate x4 mcs. Note: Config Voltage and CFGBVS is module specific and has nothing todo with the spi mode, see TE0713 schematic.
You can also check on the prm file the content of the mcs. Or read back Flash content and check.
Let me know
br
John
Thank you. I'll try to add to the xdc the code that you suggested me looking if this can solve the problem. I'll try and I'll let you know. Thanks for the help!
Thanks for the help. I solved the problem! I wait more time after FPGA strtup. With my old xdc and I needed to wait after startup that FPGA read the flash but I didn't expected that it needs of more than 20 second to start and so I thought thath it didn't work.
But after syntetising with the constranints that you suggested me me now the FPGA load the mcs from the flash instantly! Thank for the help!!