Hi,
What is the best way to program the eFuses in the Zynq on a TE0720 board on a TE0701 base board?
As far as I can see from the Xilinx documentation the Platform USBII cable is needed to program the AES key via JTAG. However it can't program the RSA hash value. The Xilinx docs (XAPP1175, UG1025) also describe using the secure key driver, which is a program that you compile and run on the Zynq with the keys added in an include file. This needs to drive the JTAG port from some MIO pins. Would I have to make a cable up that does this connection, or is it already on the base board?
Thanks
Leon
Hi
TE0701 and TE0703 both include a Carrier Controller (a small CPLD) that has all needed connectivity. And it is possible to reprogram the Carrier controller to route the MIO to JTAG.
We have not a ready design for this, but I flag it as priority for us to do and publish.
br,
Antti Lukats
Hi,
That sounds great. Do you have a timescale for this? Also would this be a new CPLD design that is only used to program the eFUSEs, with the original design replaced afterwards, or is it an upgrade to the current design.
Is it possible to get hold of the current CPLD design so that we can look at doing this ourselves?
Regards
Leon
Quote from: Leon on February 24, 2014, 02:28:24 PM
Hi,
That sounds great. Do you have a timescale for this? Also would this be a new CPLD design that is only used to program the eFUSEs, with the original design replaced afterwards, or is it an upgrade to the current design.
Is it possible to get hold of the current CPLD design so that we can look at doing this ourselves?
Regards
Leon
we will add this as easy to use configuration option, but only AFTER we have verified the UG1025 process ourself. If you drop me a email support@ I can send snapshot of current/old cpld code, adding the MIO to JTAG bypass is pretty simple there. (but as we have other features to test/implement we do not want to release an untested quick fix)
br
Antti Lukats
Is there any news on this?
Or did you manage to get the on board JTAG adapter approved by Xilinx as discussed here?:
https://forums.xilinx.com/t5/Configuration/Using-Platform-USB-Cable-not-II-to-program-efuse-not-working/td-p/677384
we have done some simple tests with TE0701, and did not see any issues, we could at least program efuse user bits.
seems 2016.x just support the digilent cable solution.
Hi,
We now just use the Xilinx USB II programming pod as this is by far the simplest method to program the eFuses and control bits.
Leon.
yes but it seems there is not even need for it, the TE0790 or onboard JTAG on TE0701, TE0703 can be used as well
Hello,
Is there any news about eFuse programming ? The Xlilinx BBRAM/eFuse programming examples use MIO pins 19 (TCK), 20 (TMS), 17 (TDI), 21 (TDO) and 11 (Mux Sel (?)).
The problem is that these pins map to ETH0 if I understand correctly, and there are not a lot of free MIO pins available...
Thanks in advance,
Christophe