as far as I know, the two CPLDs in the TEBF0808 are JTAG chained using MIO26 .. MIO29.
Does that mean if I configure one of them to use those pins for another purpose I won't be able to access them?
You can reconfigure CPLDs with your setup (our source code is available on the download area), but both CPLDs works together, so you must pay attention what you change.
And in case you mean you want use MIO for other purpose in your Vivado design, this is also possible (depends on MIO switch matrix --> See Xilinx U+ Zynq TRM) But depending on the use MIO interface you need maybe also change CPLD Firmware and you must check if the interface you has select support such a routing over cpld.
br
John
More precisely, I want to route SPI0 as follows:
Signal FPGA pin goes to routed to
SCK MIO26 U17 (MIO26) U17 (EX_IO2)
SS MIO29 U17 (MIO29) U17 (EX_IO4)
MOSI MIO31 U39 (MIO31) U39 (X6) ----> U17(X6) ---> U17 (EX_IO3)
Signals in the CPLDs are just assigned, no clock capture. I use X6 to transfer MOSI from U39 to U17.
Other uses of those signals have been commented out. Port directions are also changed for this purpose
Hi,
why did you not use EX_IO5...8 from P2 PMOD?
You must only set direction correctly on U33 (levelshifter)
See TEBF0808 Schematic page 30
--> all these signals are available on PL and instead to use MIO, route SPI over PL (select EMIO).
But, change CPLD Firmware to use EX_IO1...4 should be also possible.
br
John
Because they are connected to the PL and I want to use the PS SPI
I'm actually using one of them to send a clock for a filter, and three of the others for the SPI signals
EMIO is an option, although my main problem now is I can't access the CPLDs
Hi,
you did not answer again:
https://forum.trenz-electronic.de/index.php/topic,1224.0.html
I will install Lattice Diamond 3.11 today and will check if this can make trouble.
Maybe you should reinstall Lattice Diamond. I've also one other option, to check if it's a SW problem, but we can discuss on the other post.
br
John