As understand from the Subject, I have easy question which is "How to start project in verilog with "vivado_create_project_guimode.sh" command?" because default project HDL language is VHDL.
Hi,
normally it's not need, because Vivado can mix different languages, but in case you will still change it, you has 2 option.
- Change in Vivado Project settings after the project is generated (and regenerate also the auto generated wrapper)
or
- create a <basfolder>\settings\project_settings.tcl file and include: set_property target_language Verilog [current_project]
- --> create the project with the scripts. --> scripts loads the settings above.
See also https://wiki.trenz-electronic.de/display/PD/Project+Delivery+-+Xilinx+devices#ProjectDelivery-Xilinxdevices-UserdefinedSettings (https://wiki.trenz-electronic.de/display/PD/Project+Delivery+-+Xilinx+devices#ProjectDelivery-Xilinxdevices-UserdefinedSettings)
brJohn