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#51
UltraScale / Re: Does Trenz have Master XDC...
Last post by JH - June 28, 2024, 09:25:47 AMHi,
best way is you start with our reference design:
https://wiki.trenz-electronic.de/display/PD/TE0745+Test+Board
It's for Vivado 23.2 and includes Board files for basic PS setting and some petalinux example and also prebuilt binaries to test your HW directly.
I would recommend to use 23.2 when you start, than it's easier to use our reference design with all sources.
For PL IO, you can use AMD IO planner, correct Pin Names are available in our schematics or pinout table. IO Standard for PL IOs depends on your connected periphery (the most pins goes only to simple Pin header).
Pinout table:
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout
-->
https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Pinout/TE0745_series_pinout_tracelength.xlsx
br
John
best way is you start with our reference design:
https://wiki.trenz-electronic.de/display/PD/TE0745+Test+Board
It's for Vivado 23.2 and includes Board files for basic PS setting and some petalinux example and also prebuilt binaries to test your HW directly.
I would recommend to use 23.2 when you start, than it's easier to use our reference design with all sources.
For PL IO, you can use AMD IO planner, correct Pin Names are available in our schematics or pinout table. IO Standard for PL IOs depends on your connected periphery (the most pins goes only to simple Pin header).
Pinout table:
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout
-->
https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Pinout/TE0745_series_pinout_tracelength.xlsx
br
John
#52
UltraScale / Re: Does Trenz have Master XDC...
Last post by Reymon - June 27, 2024, 02:00:26 AMHello, I am a beginner FPGA programmer, I tried to do the same, using the XDC file (Vivado 2024.1) to configure the inputs/outputs like I do with Avnet (ZedBoard) or Digilent (Nexys 4) boards. I'm wondering if you successfully created your own XDC or 'part0_pins.xml' files for the TE0820 SOM and TE0701 carrier board. If yes, could you please tell me what procedure you followed?
I have a carrier board TEB0745-02 and TE0745-02-30-1IA SOM.
I have a carrier board TEB0745-02 and TE0745-02-30-1IA SOM.
#53
Trenz Electronic FPGA Modules / Re: FSBL hangs when initializi...
Last post by JH - June 26, 2024, 12:43:48 PMHi,
yes simple remove this part of the code for PLL programming. You will not damage the board. This part is like a example in case you want to reprogramm PLL on power up. TE0715 PLL is preprogramm with following CLKS:
https://wiki.trenz-electronic.de/display/PD/TE0715+TRM#TE0715TRM-ProgrammableClockGenerator
it's the same output CLK frequence like on the example reprogramming on runtime.
br
John
yes simple remove this part of the code for PLL programming. You will not damage the board. This part is like a example in case you want to reprogramm PLL on power up. TE0715 PLL is preprogramm with following CLKS:
https://wiki.trenz-electronic.de/display/PD/TE0715+TRM#TE0715TRM-ProgrammableClockGenerator
it's the same output CLK frequence like on the example reprogramming on runtime.
br
John
#54
Trenz Electronic FPGA Modules / TE0802 as PCIe device
Last post by CM - June 24, 2024, 07:55:11 PMHi,
I am currently working on using the TE0802 as a PCIe device with the help of an M.2 to PCIe connector breakout chain with the goal of plugging the PCIe side into the edge connector on a motherboard which takes the role of the root.
Going through the pinouts of the board, my M.2 card and the PCIe connector, I can already confirm that my grounding is fine, no shorts between the voltage supplies on both sides are happening and that the TX and RX are properly handled.
However, both the PCIe host machine as well as the TE0802 will have a conflicting reference clock on the connection.
I would like to stop the clock generator on the TE0802 to apply its signal to the M.2 connector.
There are two paths I currently see:
1) Remove the decoupling caps on the output of the CDCI6214 (C126/C172) to physically disconnect the clock generator from the connector.
I would like to avoid this because this setup will be replicated fairly often.
2) Reprogram the CDCI6214 to set the output of Channel 4 (Y4P/Y4N) to a high impedance state.
So my question boils down to:
Is it possible to reprogram the CDCI6214 on the TE0802 to stop the generation of the SSD_RCLK and if so, how would I achieve this?
Thanks a lot
Christopher
I am currently working on using the TE0802 as a PCIe device with the help of an M.2 to PCIe connector breakout chain with the goal of plugging the PCIe side into the edge connector on a motherboard which takes the role of the root.
Going through the pinouts of the board, my M.2 card and the PCIe connector, I can already confirm that my grounding is fine, no shorts between the voltage supplies on both sides are happening and that the TX and RX are properly handled.
However, both the PCIe host machine as well as the TE0802 will have a conflicting reference clock on the connection.
I would like to stop the clock generator on the TE0802 to apply its signal to the M.2 connector.
There are two paths I currently see:
1) Remove the decoupling caps on the output of the CDCI6214 (C126/C172) to physically disconnect the clock generator from the connector.
I would like to avoid this because this setup will be replicated fairly often.
2) Reprogram the CDCI6214 to set the output of Channel 4 (Y4P/Y4N) to a high impedance state.
So my question boils down to:
Is it possible to reprogram the CDCI6214 on the TE0802 to stop the generation of the SSD_RCLK and if so, how would I achieve this?
Thanks a lot
Christopher
#55
Trenz Electronic FPGA Modules / Re: FSBL hangs when initializi...
Last post by Stonebull - June 24, 2024, 01:45:51 PMHello Waldi,
sorry for my late reply, I did not see your message earlier.
I am still using the Vivado Version 2019.1 for a reason. A while ago a colleague of mine tried using the Trenz SOMs with the newest reference design, the 2022.2 which resulted in extreme problems during debugging (Stepping issues, breakpoints setting failed,...).
On his request for support, Mr. John Hartfiel could not provide us a solution, apart from telling us to go ask Xilinx for support on their faulty toolchain. Unfortunately AMD repied that they cannot give us support on outdated Tools (Vivado at the time released version 2023.x). So we were stuck, as the newest Reference Design from Trenz was (and still is) using only Vivado 2022.2.
My solution for the current problem of not being able to boot from flash anymore, was to rebuild the project from scratch from a working reference design.
Can you tell me if it is save to not program the Si5338 Clock Generator at all, in order to use the I2C1 for other stuff?
And how may I overcome the booting issue of the FSBL? Can I skip the section that blocks entirely without damaging something?
sorry for my late reply, I did not see your message earlier.
I am still using the Vivado Version 2019.1 for a reason. A while ago a colleague of mine tried using the Trenz SOMs with the newest reference design, the 2022.2 which resulted in extreme problems during debugging (Stepping issues, breakpoints setting failed,...).
On his request for support, Mr. John Hartfiel could not provide us a solution, apart from telling us to go ask Xilinx for support on their faulty toolchain. Unfortunately AMD repied that they cannot give us support on outdated Tools (Vivado at the time released version 2023.x). So we were stuck, as the newest Reference Design from Trenz was (and still is) using only Vivado 2022.2.
My solution for the current problem of not being able to boot from flash anymore, was to rebuild the project from scratch from a working reference design.
Can you tell me if it is save to not program the Si5338 Clock Generator at all, in order to use the I2C1 for other stuff?
And how may I overcome the booting issue of the FSBL? Can I skip the section that blocks entirely without damaging something?
#56
EDDP-EDPS Support / TE0950 Power consumption / Hea...
Last post by dje666 - June 24, 2024, 12:53:07 PMDear Forum,
Can anyone tell me the core temperature of the Versal device fitted to this TE0950 dev-kit when all 8 XCVRs are very active (preferably with x4 PCIe and QSFP Links running).
In my Artix US+ design it's the 8 XCVRs that are burning power and generating heat, and I need to know if the Versal family might be a lower power alternative.
Regards,
DJE666
Can anyone tell me the core temperature of the Versal device fitted to this TE0950 dev-kit when all 8 XCVRs are very active (preferably with x4 PCIe and QSFP Links running).
In my Artix US+ design it's the 8 XCVRs that are burning power and generating heat, and I need to know if the Versal family might be a lower power alternative.
Regards,
DJE666
#57
CYC1000 community projects / Re: I present a comunity of IN...
Last post by Subcritical - June 23, 2024, 03:18:45 PMMSX1FPGA
MSX1 cloned in FPGA
This project is an MSX1 cloned in FPGA, with some parts of the OCM project.
Specifications:
Multiple boards;
MSX1 50Hz or 60Hz;
RAM Mapper size configurable, depends on the board;
128K Nextor (MSX-DOS2 evolution) ROM with SD driver;
Megaram SCC/SCC+ from OCM project (size configurable, depends on the board);
Keyboard map reconfigurable;
Simple switched I/O ports (no software yet);
15/31KHz configurable.
Scanlines configurable.
HDMI output on some boards.
In the project there is a loader (IPL) to boot and load ROMs and configuration from SD card.
The "CONFIG.TXT" configuration file is self-explanatory.
You can see the MSX1FPGA here playing KONAMI KING'S VALLLEY:
MSX1 cloned in FPGA
This project is an MSX1 cloned in FPGA, with some parts of the OCM project.
Specifications:
Multiple boards;
MSX1 50Hz or 60Hz;
RAM Mapper size configurable, depends on the board;
128K Nextor (MSX-DOS2 evolution) ROM with SD driver;
Megaram SCC/SCC+ from OCM project (size configurable, depends on the board);
Keyboard map reconfigurable;
Simple switched I/O ports (no software yet);
15/31KHz configurable.
Scanlines configurable.
HDMI output on some boards.
In the project there is a loader (IPL) to boot and load ROMs and configuration from SD card.
The "CONFIG.TXT" configuration file is self-explanatory.
You can see the MSX1FPGA here playing KONAMI KING'S VALLLEY:
#58
Trenz Electronic FPGA Modules / TE0820+HDMI701
Last post by PaulChang - June 21, 2024, 09:41:01 AMDear Sir,
I would like to try this TE0820+HDMI701 demo.
Vendor Part number of TE0820 is TE820-04-2BE21MA.
Copy Petalinux image.ub and Boot.bin on SD-Card
\HDMI701\prebuilt\boot_images\2eg_1e_2gb\u-boot\BOOT.bin
\HDMI701\prebuilt\os\petalinux\2GB\image.ub
It does not has image on monitor and it seems stuck.
Please see the attach file.
Any Suggestion?
Best Regards,
Paul
I would like to try this TE0820+HDMI701 demo.
Vendor Part number of TE0820 is TE820-04-2BE21MA.
Copy Petalinux image.ub and Boot.bin on SD-Card
\HDMI701\prebuilt\boot_images\2eg_1e_2gb\u-boot\BOOT.bin
\HDMI701\prebuilt\os\petalinux\2GB\image.ub
It does not has image on monitor and it seems stuck.
Please see the attach file.
Any Suggestion?
Best Regards,
Paul
#59
Open source hardware / TE0890 SPI ELF Bootloader
Last post by Mantas - June 20, 2024, 10:38:57 PMTE0890 SPI ELF Bootloader - remove from project.
how disable, remove ELF, i don't wana use it ? I remove ELF from vivado (only left mb_bootlauder_le.elf), but i don't understand how vitis get it. With this bootlauder don't work vitis debug tools, and don't run any code.
how disable, remove ELF, i don't wana use it ? I remove ELF from vivado (only left mb_bootlauder_le.elf), but i don't understand how vitis get it. With this bootlauder don't work vitis debug tools, and don't run any code.
#60
Trenz Electronic FPGA Modules / Re: TEM0009 module
Last post by JH - June 20, 2024, 10:16:56 AMHi,
step model is available on the download area of the module.
Use the download tap on the product page an navigate to Rev02/HW_Design folder or use this link:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/JTAG_Programmer/TEM0009/REV02/HW_Design
br
John
step model is available on the download area of the module.
Use the download tap on the product page an navigate to Rev02/HW_Design folder or use this link:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/JTAG_Programmer/TEM0009/REV02/HW_Design
br
John