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EDDP-EDPS Support / TE0950 Power consumption / Hea...
Last post by dje666 - June 24, 2024, 12:53:07 PM
Dear Forum,

Can anyone tell me the core temperature of the Versal device fitted to this TE0950 dev-kit when all 8 XCVRs are very active (preferably with x4 PCIe and QSFP Links running).

In my Artix US+ design it's the 8 XCVRs that are burning power and generating heat, and I need to know if the Versal family might be a lower power alternative.


CYC1000 community projects / Re: I present a comunity of IN...
Last post by Subcritical - June 23, 2024, 03:18:45 PM
MSX1 cloned in FPGA

This project is an MSX1 cloned in FPGA, with some parts of the OCM project.


Multiple boards;
MSX1 50Hz or 60Hz;
RAM Mapper size configurable, depends on the board;
128K Nextor (MSX-DOS2 evolution) ROM with SD driver;
Megaram SCC/SCC+ from OCM project (size configurable, depends on the board);
Keyboard map reconfigurable;
Simple switched I/O ports (no software yet);
15/31KHz configurable.
Scanlines configurable.
HDMI output on some boards.
In the project there is a loader (IPL) to boot and load ROMs and configuration from SD card.

The "CONFIG.TXT" configuration file is self-explanatory.

You can see the MSX1FPGA here playing KONAMI KING'S VALLLEY:
Trenz Electronic FPGA Modules / TE0820+HDMI701
Last post by PaulChang - June 21, 2024, 09:41:01 AM
Dear Sir,

I would like to try this TE0820+HDMI701 demo.
Vendor Part number of TE0820 is TE820-04-2BE21MA.

Copy Petalinux image.ub and Boot.bin on SD-Card


It does not has image on monitor and it seems stuck.
Please see the attach file.
Any Suggestion?

Best Regards,
Open source hardware / TE0890 SPI ELF Bootloader
Last post by Mantas - June 20, 2024, 10:38:57 PM
TE0890 SPI ELF Bootloader - remove from project.

how disable, remove ELF, i don't wana use it ? I remove ELF from vivado (only left mb_bootlauder_le.elf), but i don't understand how vitis get it. With this bootlauder don't work vitis debug tools, and don't run any code.
Trenz Electronic FPGA Modules / Re: TEM0009 module
Last post by JH - June 20, 2024, 10:16:56 AM
step model is available on the download area of the module.
Use the download tap on the product page an navigate to Rev02/HW_Design folder or use this link:
Trenz Electronic FPGA Modules / Re: FSBL hangs when initializi...
Last post by Waldi3141 - June 18, 2024, 04:07:03 PM
Hello Stonebull,

can you try our latest 2022.2 reference design?

I just flashed the hello_te0715 BOOT.bin file to the onboard qspi flash and it boots and programs the PLL just normal on the TE0701. You can use the prebuilt file from our 2022.2 project and try it out without rebuilding anything.

Also, you might need to update the TE0715 CPLD firmware

best regards
Trenz Electronic FPGA Modules / TEM0009 module
Last post by midlandsscud - June 14, 2024, 06:30:11 AM
Can you please provide a .stp file for the TEM0009 module?
Trenz Electronic FPGA Modules / FSBL hangs when initializing S...
Last post by Stonebull - June 13, 2024, 09:37:56 PM
I am using a TE0715 together with the TE0701 carrier board with Vivado 2019.1. I started my project based on the supplied reference project from trenz for the specific board.

I am having problems getting any program to boot from flash lately and I just cannot figure out what's wrong. I run bare-metal software on the ARM cortex A9.
For simplicity I tried with the simple trenz_hello_world project, which I successfully flashed onto the SoM, but during boot the FSBL(trenz modified) hangs with the following output:

Xilinx First Stage Boot Loader (TE modified)
<\r>Release 2018.3<9>Jun 13 2024-15:58:55<\r>
Device IDCODE: 373B093<\r>
Device Name: 7z015 (1B)<\r>
Device Revision: 0 <\r>
TE0715 TE_FsblHookBeforeHandoff_Custom<\r>
Configure TE715 SI5338<\r>
Si5338 Init Registers Write.<\r>
Si5338 Hard reset done.<\r>

I left all FSBL(trenz_modified) files untoutched except for enabling the DEBUG_INFO switch and adding a few more p_print() for more info about when the fsbl fails.

int si5338_init(unsigned char chip_addr)
int i;
u8 reg_val;
Reg_Data rd;
int Status;

    //p_printf(("Si5338 Init Start.\r\n"));
    p_printf(("Si5338 Init Registers Write.\r\n"));

// I2C Programming Procedure
iic_write8( chip_addr, 246, 0x01); //Hard reset
p_printf(("Si5338 Hard reset done.\r\n"));

// Disable Outputs
iic_write8_mask( chip_addr, 230, EOB_ALL, EOB_ALL); // EOB_ALL = 1
p_printf(("Si5338 Disable Outputs done.\r\n"));

// Pause LOL
iic_write8_mask( chip_addr, 241, DIS_LOL, DIS_LOL); // DIS_LOL = 1
p_printf(("Si5338 Pause LOL done.\r\n"));


Judging from the output I'd say that the fsbl is not able to communicate with the clock generator.

Maybe it is worth mentioning that I've removed and later re-added the I2C1 from the design.
I noticed too late that the I2C1 resource is actually used during boot, but as I re-added it to the MIO pins 48/49 like it was before, I guess that should not be the problem now.

Does anybody have any ideas on how to proceed?
Any help is appreciated.
There is a topic where tells how to config a 93C56 memory attached to the FT4232 chip in the FlashPro5 programmer.

I have a FT2232 board and I config this as topic tells. My board recognized by the FPExpress as a FlashPro5 programmer. But the Ping command runs with an error:
"warpFtdi_FT_OpenEx - Port D".

The FT4232H chip has four ports and the FT2232 has only two ports. Obviously the FPExpress try to use the PORT D that the FT2232 does not have.

But your TEM0001 devboard use the FT2232 chip with PORT A!

So, how to config the FT2232 to turn it to the FlashPro5?
Trenz Electronic FPGA Modules / Re: TE0715 QSPI boot not worki...
Last post by JH - May 31, 2024, 08:47:28 AM
Good to hear that it works know.
Some note regarding PGOOD: This is a multifunction pin and used also as addition boot mode Pin now. (PGOOD output and as boot Mode input) to allow JTAG only boot mode, which is necessary for newer Vivado Versions to programm QSPI Flash, see: