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Quote from: blipton on April 27, 2024, 06:16:45 AMSoftConsole/Eclipse works fine to Flash the elf to the SMF2000 device..  but I need to read the NVM and save it to a file.

And while a dump_image seems to exist for OpenOcd 0.10 
( )

Telnetting to port 4444 doesn't work, but 3334 does.. which makes me think that the only way to get to openocd is thru 'fpserver'?

Any suggestions?
Hi I'm a new member and have the same question. Any solution?
EDDP-EDPS Support / Re: TE0950 Power consumption /...
Last post by M Kirberg - July 10, 2024, 07:57:56 AM

Versal has new and good power estimation tools - did you try these?

Open source hardware / Re: TE0890 SPI ELF Bootloader
Last post by MA - July 09, 2024, 12:49:43 PM
I can't understand exactly what you are doing. The reference design provided by Trenz generates the following 2 elf-files:
  • hello_te0890.elf
  • spi_bootloader.elf

elf-files are the software application files for zynq or MicroBlaze Processor Systems. They will be generated with Vitis. You can find an older manual for Vitis in the following link
Trenz Electronic FPGA Modules / Re: TE0720 issue
Last post by MA - July 09, 2024, 12:16:14 PM

Why not delete the memory once again?
Trenz Electronic FPGA Modules / TE0720 issue
Last post by carefullythe - July 09, 2024, 06:39:30 AM

At some point I must have programmed the QSPI with U-Boot. Now every time I try to run a test app from Vitis I see U-Boot start. Sometimes my test app will run after it but usually it does not.
CYC1000 community projects / Re: I present a comunity of IN...
Last post by Subcritical - July 08, 2024, 05:06:59 PM
In the following Video the atlas is also faithful to the original CGA in its "COMPOSITE VIDEO" mode.
With PAL format which in an expanded form reaches 512 Colors.

You can see Core PC XT, Area 5150 CGA Demo for the IBM PC by CRTC+Hornet

And the code of this core:

PAL wrapper:
Trenz Electronic FPGA Modules / Re: TE0820 -03 and -04 MODE Pi...
Last post by JH - July 08, 2024, 11:04:56 AM
with default CPLD Firmware it's on both Versions(table row has swapped only):
Mode Pin Low: SD Card
Mode Pin High QSPI Flash
Table has only switch the columns.

Module which was delivered since June 2022, we have extended bidirectional Pin PGOOD also as Boot Mode for default CPLD Firmware.

In case PGOOD is set low on power up, than JTAG only boot mode is selected
See also:

JTAG Boot and eMMC boot Mode can be selected now.
As long as PGOOD Pin is high, it's like older firmware, so it should be backward compatible.

Regarding Floating Pins:
Mode Pin and PGOOD has week pullup on the module, but you should not keep it floating.
See 4x5 Controller Pins:


Trenz Electronic FPGA Modules / TE0820 -03 and -04 MODE Pin
Last post by anatolewilson - July 08, 2024, 08:50:22 AM
We are using TE0820-03 and will be using -04 soon.
I was looking at TRM for both configurations and MODE pin setting Table 2 in -04 is reverse of -03.
Has Trenz actually changed this?
Second question, is it actually fine to float the MODE pin if booting from QSPI?
Trenz Electronic FPGA Modules / Re: TE0820+HDMI701
Last post by PaulChang - July 08, 2024, 04:06:59 AM
Hi John,

1.Waveshare 10.1inch HDMI LCD B 1280×800 IPS Touch Screen.
2.MSI optix MPG341CQR
please see the atthach file,thanks.

Best Regards
Trenz Electronic FPGA Modules / Re: TE0802 as PCIe device
Last post by garliciris - July 04, 2024, 11:19:57 AM
To stop the generation of the SSD_RCLK signal from the CDCI6214 on the TE0802 module, you would typically need to reprogram the configuration of the CDCI6214 IC itself. The CDCI6214 is a clock generator/synchronizer IC that can be configured via its control inputs to output various clock signals. That's what advice I can give you