Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: dianfeng1995 on October 31, 2020, 07:59:07 AM

Title: TE0741 clocking problem
Post by: dianfeng1995 on October 31, 2020, 07:59:07 AM
My board is not working properly now. I connect the clock to BUF and output it. I use an oscilloscope to observe that the waveform is always high level.I downloaded the circuit to Flash before, and then the clock didn't. Will it damage the clock pin?
Title: Re: TE0741 clocking problem
Post by: JH on November 02, 2020, 08:09:16 AM
which clock did you use in your design?

We offer an reference design, where you can monitor some CLKs with debugging core:
https://wiki.trenz-electronic.de/display/PD/TE0741+Test+Board#TE0741TestBoard-VivadoHWManager:

br
John
Title: Re: TE0741 clocking problem
Post by: dianfeng1995 on November 02, 2020, 08:14:56 AM
Clock use PLL Clock 0, default frequency is 100 MHz. Pin is E23/F22.
Title: Re: TE0741 clocking problem
Post by: JH on November 02, 2020, 08:19:42 AM
Our reference design use this clk also for microblaze. Lock signal of the internal mmcm which depends on this PLL CLK is connected also to the VIO core.
Please try out our reference design. There are prebuilt binaries included.
br
John
Title: Re: TE0741 clocking problem
Post by: dianfeng1995 on November 02, 2020, 08:27:39 AM
I have tried this and nothing has happened because the clock is always high and can't drive any circuits.
I tried lighting an LED light without using a clock and it was ok.
I would like to use another clock GTX REFCLK1 generated by PLL, but Vivado will report an error when implementing the integration.
The errors are as follows:
[Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid ["C:/Users/Yang/Desktop/test_410t/project_1.srcs/constrs_1/new/io_constraints.xdc":20]
[DRC UCIO-1] Unconstrained Logical Port: 1 out of 4 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: sys_clk_p.
Title: Re: TE0741 clocking problem
Post by: JH on November 02, 2020, 11:33:12 AM
Hi,
Quote
I have tried this and nothing has happened because the clock is always high and can't drive any circuits.
Our reference design didn't start? You did not see the VIO core on Vivado HW Manager when you program the prebuilt design? This must work otherwise you has some problem on your board.



Quote
I would like to use another clock GTX REFCLK1 generated by PLL, but Vivado will report an error when implementing the integration.
You must use special buffer in Vivado to route MGT REF CLK into Fabric, see our reference design.

br
John