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TE0720/TE0706 based design

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bigguiness:
Hello,

I'm working on a design using a TE0720 SoC that is based on the TE0706 carrier board since I require two Ethernet ports.

I have a couple questions on the block diagram of the te0720-eth706.xpr project.

1) Is the Concat/Labtools Frequency Counter/VIO/Utility Vector Logic part necessary or is that part of the block design strictly debug stuff?

2) Is the TE0720 System Controller I/O necessary? I assume that is is in order to connect the CPLD on the TE0720 to the Zynq. Is that IP available? When I start a new design I can't find it in the IP library.

3) I assume that the Constant block connected to the ETH_CONFIG[0:0] port is for the Ethernet PHY on the TE0720 and is needed. Correct?

4) I am a bit confused by the FCLK_CLK0 and FCLK_CLK1 outputs of the Zynq7 block. FCLK_CLK0 is set for 100MHz, FCLK_CLK1 is set for 200MHz. FCLK_CLK0 is only connected to the stuff in 1) above. FCLK_CLK1 is connected to the "slowest_sync_clk" of the Processor System Reset block and the "clkin" of the Gmii to Rgmii block for Ethernet 2. Shouldn't the Processor System Reset use the 100MHz clock?

Thanks for any help

Waldi3141:
Hi bigguiness,

1) This part allows monitoring/controlling the VIO-connected signals in the hardware manager during runtime. These blocks are not necessary for the correct functionality of this design, except the control signal ETH_RST output should stay to be able to reset ethernet manually via vio.

2) The system controller does a bunch of stuff as stated in the TRM:
https://wiki.trenz-electronic.de/display/PD/TE0720+TRM#TE0720TRM-SystemControllerCPLDI/OPins
so, yes, that has to stay. The IP is available in the provided Reference Design TE0720-ETH0706 under „ETH706/ip_lib“ in the main project directory.
Just add this ip directory to your new project and you should be able to use them in your block design.

3) It is the hardware configurartion pin of the ETH PHY on the carrier, you can trace it back using the schematics. Yes, needed.

4) the FCLK_CLK1 drives the actual Design in the PL and is necessary for the gmii2rgmii IP, so the system reset uses the same clock. FCLK_CLK0 is only for monitoring the inputs of the VIO block, it can be omitted.

Hope this helps  :)

bigguiness:
Thanks for the reply and information.

I have a couple other questions about the TE0720 and TE0706.

1) There are a number of IO pads on the XC7Z020 that are either tied directly to GND or are looped back to other IO pads. Do I need to account for these connections in any way? BTW, what are these looped back connections for?

2) Is the CLK_125MHz signal from the PHY on the TE0720 fed back to the Zynq somehow? I only see it going to the CPLD.

3) On the TE0706, the CLK125 from the PHY is fed back to the TE0720/Zynq on JB3. Is this just for convenience?

4) What is the TE0720 M1.8VOUT current capacity? Is it enough to power the second PHY or do you recommend a separate 1.8V supply? With the EN5311QI being discontinued I am having trouble finding something that will work in the space I have available.

Thanks,
Hartley

Waldi3141:
Hi Hartley,

1) Of what IO pads are you speaking exactly?

2) i advise you to read this page for information on the clocks and settings of the cpld: https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD

Per default CLK_125MHZ is connected to the zynq as XCLK. The XCLK is mapped to CLK_125MHZ and this mapping depends on the content of register CR2[15:12].

3) What do you mean? This clock is used in the reference design → set_property PACKAGE_PIN L18 [get_ports {gmii_clk_0}]

4) It depends on your custom FPGA Design and how much more is attached to your system, but yes, it should be enough to power a 2nd phy. The MPM3834CGPA can deliver up to 3A output current.

bigguiness:
Hello,

> 1) Of what IO pads are you speaking exactly?

The schematic shows these connections on the XC7Z020-1CLG484C (U5) that I am curious about:

1) T21 (IO_L1P_T0_33) is grounded.
2) V14 (IO_L19P_T3_33), W15 (IO_21P_T3_DQS_33), Y15 (IO_L21N_T3_DQS_33), Y14 (IO_L22P_T3_33), and AA14 (IO_L22N_T3_33) are connected together.
3) V13 (IO_L20P_T3_33) is connected to W13 (IO_L20N_T3_33).
4) Y13 (IO_L23P_T3_33) is connected to AA13 (IO_L23N_T3_33).
5) AB14 (IO_L24N_T3_33) is connected to AB15 (IO_L24N_T3_33).
6) H17 (IO_0_35) is connected to H18 (IO_25_35).

None of these pads go to the connectors. But I was wondering if I need to account for them for any reason and why they are connected this way.

> 2) i advise you to read this page for information on the clocks and settings of the cpld: https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD

I will review that information and let you know if I have any other questions.

> 3) What do you mean? This clock is used in the reference design → set_property PACKAGE_PIN L18 [get_ports {gmii_clk_0}]

I will review the TE0720/TE0706 reference design again.

> 4) It depends on your custom FPGA Design and how much more is attached to your system, but yes, it should be enough to power a 2nd phy. The MPM3834CGPA can deliver up to 3A output current.

Great. The only 1.8V devices in my design is the 2nd PHY and the SDIO port expander for the SD Card. The 3A current will be more than enough.

Thanks for the help,
Hartley

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