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#71

Trenz Electronic FPGA Modules / Re: Slow QSPI on TE0720: "Warn...

Last post by AaronB - November 23, 2023, 04:57:07 AM

Vivado 2018.1 and Petalinux 2019.1

#72

Trenz Electronic FPGA Modules / Re: Slow QSPI on TE0720: "Warn...

Last post by M Kirberg - November 22, 2023, 04:04:04 PM

Hi,

that is strange, what versions of tools are you on?

br

#73

Trenz Electronic FPGA Modules / Re: TE0890 - Power Consumption...

Last post by gathertearful - November 22, 2023, 10:56:41 AM

I also have the same problem. I found the answer the best until I read your article. I tried pulling the CS0 signal high to turn off the IC and it worked fine. Thank.

#74

Trenz Electronic FPGA Modules / Slow QSPI on TE0720: "Warning:...

Last post by AaronB - November 21, 2023, 06:43:58 PM

Any tips on getting the QSPI boot to use the correct clock frequency when booting petalinux from QSPI?

I'm using a TE0720, the boot code shows "SoM: TE0720-00-0C  F SC REV:00"

Its installed on a custom board, and I'm trying to boot petalinux from QSPI.

eMMC boot is fast, but I can't do that because the system won't boot if there is no Micro SD card in the slot, due to the "voltage select" issue.  Having a placeholder micro SD card in the slot at all times is not an option for my use case.  I have had success with removing the external SD card from my hardware configuration, but I'm trying to avoid that if possible.

So now I'm trying QSPI booting, but it seems really slow. 

During boot, there is a warning about clock speed limited to 100kHz, followed by a long pause while the flash is read.  It takes 4 seconds to load a 12MB image.ub file, which is slower than my requirements will allow.

At the uboot command prompt, I can manually force a 50 MHz clock speed, and it loads in 2 seconds, which is better.

However, I'd like to know if there is something I can do to ensure faster QSPI clock speeds.

The Vivado config for the QSPI speeds is attached, and the device tree snippet that was automatically generated is shown below.  Note that it shows a max clock speed of 50Mhz (0x2faf080).

Code Select Expand

                spi@e000d000 {
                        clock-names = "ref_clk", "pclk";
                        clocks = <0x1 0xa 0x1 0x2b>;
                        compatible = "xlnx,zynq-qspi-1.0";
                        status = "okay";
                        interrupt-parent = <0x4>;
                        interrupts = <0x0 0x13 0x4>;
                        reg = <0xe000d000 0x1000>;
                        #address-cells = <0x1>;
                        #size-cells = <0x0>;
                        is-dual = <0x0>;
                        num-cs = <0x1>;
                        spi-rx-bus-width = <0x4>;
                        spi-tx-bus-width = <0x4>;

                        flash@0 {
                                compatible = "jedec,spi-nor";
                                reg = <0x0>;
                                #address-cells = <0x1>;
                                #size-cells = <0x1>;
                                spi-max-frequency = <0x2faf080>;

                                partition@0x00000000 {
                                        label = "boot";
                                        reg = <0x0 0x500000>;
                                };

                                partition@0x00500000 {
                                        label = "bootenv";
                                        reg = <0x500000 0x20000>;
                                };

                                partition@0x00520000 {
                                        label = "kernel";
                                        reg = <0x520000 0xc10000>;
                                };

                                partition@0x01130000 {
                                        label = "data";
                                        reg = <0x1130000 0xed0000>;
                                };
                        };
                };


If I manually stop at the uboot prompt and measure things, I can MANUALLY configure the subsystem with a 50 Mhz clock.  How can I get this by default?

Here are some example uboot logs.
First, the default one I get by allowing the boot to continue on its own.  the read takes 4 seconds:

Code Select Expand

[2023-11-21 11:32:17.373] Hit any key to stop autoboot:  0
[2023-11-21 11:32:17.376] Warning: SPI speed fallback to 100 kHz
[2023-11-21 11:32:17.380] SF: Detected n25q256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB
[2023-11-21 11:32:17.387] device 0 offset 0x520000, size 0xc10000
[2023-11-21 11:32:21.448] SF: 12648448 bytes @ 0x520000 Read: OK

Next, one where I manually specify the speed option to 50Mhz, and it takes 2 seconds:

Code Select Expand


[2023-11-21 11:37:46.725] Zynq> sf probe 0 50000000
[2023-11-21 11:37:54.960] SF: Detected n25q256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB
[2023-11-21 11:37:54.968] Zynq> boot
[2023-11-21 11:38:01.401] SF: Detected n25q256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB
[2023-11-21 11:38:01.407] device 0 offset 0x520000, size 0xc10000
[2023-11-21 11:38:03.446] SF: 12648448 bytes @ 0x520000 Read: OK


Finally, one where I manually set the speed to 100Khz as a comparison, and the read takes 4 seconds as we might expect:

Code Select Expand

[2023-11-21 11:39:10.933] Zynq> sf probe 100000
[2023-11-21 11:39:21.905] SF: Detected n25q256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB
[2023-11-21 11:39:21.912] Zynq> boot
[2023-11-21 11:39:25.408] SF: Detected n25q256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB
[2023-11-21 11:39:25.415] device 0 offset 0x520000, size 0xc10000
[2023-11-21 11:39:29.477] SF: 12648448 bytes @ 0x520000 Read: OK


For the moment I will try manually overriding the u-boot variable that loads the kernel into memory and does an "sf probe 0".  If I change this to "sf probe 0 50000000", this may accomplish my goal, but I'm confused as to what might be going wrong in my configuration that requires this.

#75

Trenz Electronic FPGA Modules / Re: TE0705 USB over-current si...

Last post by mgillott - November 21, 2023, 02:44:25 PM

Found the source for the CPLD !

The USB_OC signal and a few other signals are read by an I2C interface configured on MIO10 and MIO11 of the connected module.

So  I imagine these signals are actually not used unless a suitable driver is created for these GPIOs ?

Malc

#76

Trenz Electronic FPGA Modules / TE0705 USB over-current signal...

Last post by mgillott - November 21, 2023, 01:21:20 PM

Where does the CPLD route the USB_OC signal

Thanks
Malc

#77

Trenz Electronic FPGA Modules / Re: S7Mini program flash

Last post by salmawisoky - November 20, 2023, 06:08:04 AM

To load the flash of S7Mini using a TCL script, you can follow these steps:

1. Generate the bitstream file: Use Vivado to generate the bitstream file (.bit) for your design using the "write_bitstream" command. Make sure to include the necessary configuration options for the Spartan-7 FPGA on the S7Mini board.

2. Select the flash device: In Vivado, you need to select the appropriate flash device for programming. The n25q64-3.3v-spi-x1_x2_x4 is a common flash device used in many boards. You can confirm if this is the correct flash device for your S7Mini board by referring to the board's documentation or specifications.

3. Generate a programming file: To load the bitstream into the flash, you need to generate a programming file (.mcs or .bin) that combines the bitstream with the necessary configuration data for the flash device. This file defines the format and contents to be written to the flash memory.

4. Use the TCL script: Write a TCL script that automates the programming process. Within the script, you can use the Vivado TCL commands to specify the flash device, load the bitstream file, and generate the programming file.

Here's an example of the TCL script to load the flash:

```
# Set the flash device
set_property PROGRAM.BLANK_CHECK  0 [get_mfg_parts "n25q64-3.3v-spi-x1_x2_x4"]

# Load the bitstream
set_property BITSTREAM.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33MHZ [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-2 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]

# Generate the programming file
write_cfgmem -force -format MCS -size 16 -interface SPIx4 -loadbit "up 0x0 <bitstream_file.bit>" -file "output_file.mcs"
```

Replace `<bitstream_file.bit>` with the path to your generated bitstream file. The script sets the flash device properties, configures the bitstream settings, and generates the programming file in MCS format.

Make sure to customize the script based on your specific configuration and flash device requirements. You can execute the TCL script within the Vivado TCL console or run it using the Vivado batch mode.

Remember to refer to the Vivado documentation and the S7Mini board documentation for detailed information on flash programming and configuration settings specific to your board.

[Question:]

#78

UltraScale / TE0820 POR with JTAG TE0790

Last post by pema - November 17, 2023, 09:12:50 AM

Hi there,
Question: How to POR the TE820 after flashing it, without physical interaction?
Problem Description: Every time after flashing the TE820 eMMC I need to perform a POR over the RESIN signal line (Connector JM2 Pin 18). This can be either over the push button on the Carrier board or with a full power reset.

I have tried already all kinds of reset over the XSCT but none of them seems to work. So I normally, just have one of those cheap wifi  power plugs connected to the TE820 to perform a POR( by power OFF power ON).

Is there any other way to perform this without needing to press the Push button or Power boot? Perhaps a signal line from the TE0790 to perform the POR ? ( I could solder a wire to the Carrier board) XMOD E and XMOD G are still free. Would it be possible to provide the code to the CPLD in the TE0790 or modify it in order to provide a SRST signal over XSCT?

Many Thanks  and have a nice weekend .

#79

UltraScale / Reference Design & Custom Usag...

Last post by jwil - November 16, 2023, 08:17:36 PM

Hello, I am in the process of bringing up the 2022.2 Reference Design for the TE0818 SOM +TEBF0818 Carrier. I would like to know more about the default configuration of the SI5345 that is onboard the TE0818 SOM. I have located the associated SkyWorks SI5345 slabtimeproj file in the reference design and have viewed it in ClockBuilderPro.

Is there documentation or a breakdown of how each output port is being used by the SOM under the provided project?

Are there input and output ports specifically left unused for designs to source / consume from off-board? If so, how many, and which ones?

Any other pointers to consider regarding use of the onboard SI5345 are welcome.

Thanks in advance.

#80

Trenz Electronic FPGA Modules / Re: TE0890 - Power Consumption...

Last post by Vadim Y - November 16, 2023, 10:15:01 AM

Hello cjc220,

The TE0890 contains no control signals that could disable unused power supplies or delay FPGA configuration.

In the old datasheet of HyperRam U2 there is a note that in Power On Reset mode it consume about 50mA. I would recommend to pull the signal CS0 high to turn off the IC.

https://www.issi.com/WW/pdf/66-67WVH8M8ALL-BLL.pdf

Best regards,
Vadim