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Trenz Electronic FPGA Modules / Re: Petalinux Build [Errno 32] Broken Pipe
« Last post by DR on December 05, 2022, 05:20:05 PM »
Yes Markus,
Thanks again for the help.
and - Yes I tried various permutations of the patches on bitbake - most of them wound up breaking with many dependencies that relied on other patches that were incompatible with the current version that I was using.
When I tried to use the latest version of everything from master together, then many other dependencies were broken deeper in. It was a painful experience. Especially since so many files had to be manually fixed to accommodate the current libraries. Then checksums were broken ... what a mess.
Dave
:*^)
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UltraScale / Re: Upgrade Toolchain 2019.2 to 2021.2: Petalinux Build Errors
« Last post by M Kirberg on December 05, 2022, 10:35:59 AM »
Do you have any more logs for the Build output of the specific recipe? (u-boot-xlnx?)

The logs you posted are not very helpful.


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Trenz Electronic FPGA Modules / Re: Petalinux Build [Errno 32] Broken Pipe
« Last post by M Kirberg on December 05, 2022, 09:27:17 AM »
For clarity: the dependency actually set by the Yocto Project not by Xilinx itself, for petalinux 2021.2 == Yocto Gatesgarth this is:

https://docs.yoctoproject.org/gatesgarth/ref-manual/ref-system-requirements.html

Petalinux is an additional layer which has its own dependencies, but your error seems clearly caused by the former one.

Ok a pity that this patch is not working.
I mean the error message suggest that it bitbake-worker is at fault

You can additionally try to find patches in the history of files, e.g. here
https://github.com/yoctoproject/poky/commits/master/bitbake/bin/bitbake-worker
and apply them selectively.
Or even try to use the latest version from master and see if that is any good.

Best
Markus
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Trenz Electronic FPGA Modules / Re: Petalinux Build [Errno 32] Broken Pipe
« Last post by JH on December 05, 2022, 07:50:12 AM »
Hi,
Quote
Plus, eventually, it seems like this is going to need a solution as more people use Ubuntu 22?
you are right, but petalinux is provided by AMD(Xilinx), and they only support selected Linux distribution....
For 2022.2 it's at the moment only:
https://docs.xilinx.com/r/en-US/ug1144-petalinux-tools-reference-guide/Installing-the-PetaLinux-Tool
  • Red Hat Enterprise Workstation/Server 7.4, 7.5, 7.6, 7.7, 7.9, 8.2 (64-bit), 8.3, 8.4, 8.5, 8.6
  • CentOS Workstation/Server 7.4, 7.5, 7.6, 7.7, 7.9
  • Ubuntu Linux Workstation/Server 18.04.1, 18.04.2, 18.04.3, 18.04.4, 18.04.5, 18.04.06, 20.04, 20.04.1, 20.04.2, 20.04.3 ,20.04.4 (64-bit)
  • SUSE Linux 15.2
only AMD(Xilinx) can changes this...
br
John
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Trenz Electronic FPGA Modules / Re: Petalinux Build [Errno 32] Broken Pipe
« Last post by DR on December 02, 2022, 11:04:21 PM »
Thanks much for the hint and looking into this with me ...

I tried the patch to bitbake-worker - which looked like it might solve my problem, but unfortunately, no - still getting the same "Failed to spawn fakeroot worker" [Errno 32] Broken pipe.

Anyone else see this or have any ideas.

I would like to stick to Ubuntu 20 as suggested, but our systems forbid network bridging, which is required for such a Docker.

Plus, eventually, it seems like this is going to need a solution as more people use Ubuntu 22?

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Trenz Electronic FPGA Modules / Re: TE0715 constraint and board files question
« Last post by JH on December 02, 2022, 12:24:02 PM »
Hi,
You can' compare FPGA and SoC microcontroller and so...with the FPGA or SoC with FPGA there are much more freedom margins.
TE0701 itself is a carrier where you can place different Modules.
TE0715 is a module where  you can used different carriers....and everything is configurable.
For beginner, normally a Evaluation board is much better than Module carrier solution with generic documentation.
But for your combination.
At frist, please send me ther serial number of your TE0715. Depending on the assembeld SoC, it  can happends that you must pay attention with TE0701 DIP and Jumper configuration.
There are TE0715 available which have IOs which supports max 1.8V and in this case TE0701 must be set up for variable bank powers 1.8V
We have scribt based reference design for with basic examples and binaries for our TE0715:
https://wiki.trenz-electronic.de/display/PD/TE0715+Test+Board
--> easiest way to start is to use prebuilt binaries and boot from SD (put files to fat32 partion on SD Card)
This designs can be used on TE0715 and TE0701. But you must select your correct assembly variant (different assembly variants need different configuration...).
Generic TE0701 and generic TE0715 HW description:
https://wiki.trenz-electronic.de/display/PD/TE0715+TRM
https://wiki.trenz-electronic.de/display/PD/TE0701+TRM
and some overview
https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Carriers
https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Integration+Guide


I know it's a lot of documentation and theoretically you must also read Xilinx documentation for 7 series Zynq....
Unfortunally we can't give full support for beginner, but ask some question if need an we can will see.


br
John
br
John
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Trenz Electronic FPGA Modules / Re: TE0715 constraint and board files question
« Last post by gswdh on December 02, 2022, 12:13:20 PM »
I'm no expert in the FPGA SoM market however I think it would be better for manufacturers to reduce the number of product variations and have more thorough support for the those products, it would make them far stronger in value vs the rest of them. There's a million microcontroller and Linux SBCs but the reason Arduino and Raspberry dominate in their respective category is documentation and support...
8
Thanks for pointing to the solution :)
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Trenz Electronic FPGA Modules / Re: TE0715 constraint and board files question
« Last post by Waldi3141 on December 02, 2022, 12:03:43 PM »
Hi, we are trying our best to provide a comprehensive documentation for our boards, but it almost impossible to do that for every carrier + module configuration, simply because we offer so many variations. Therefore i can relate that it is not the easiest thing to get your application running. But we are here to help  :)
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EDDP-EDPS Support / Re: How to initialize the EDDP by BTN3
« Last post by Andrei Errapart on December 02, 2022, 10:06:33 AM »
Hi Jason Bourne,


There are several projects demonstrating working with the EDDP.

Assuming you are trying to open the project in the folder "IIoT-EDDP/HLS/ARTY_Z7_FULL", you have to use Vivado 2017.1 for that. In this project, FOC is implemented as multiple IP core blocks developed in HLS. When writing one of the previous answers, I had Block Design in this project opened for the reference.

For the project in the folder "SDSoC", Vivado SDSoC 2017.1 is required. In this project, FOC is implemented as a single HLS IP core in a SDSoC project. The source for this can be found in the file "foc.cpp". In the block design of the SDSoC project, the internals of this IP core are not visible.

In the folder "Vitis", one can find Xilinx Vitis project. The FOC is again implemented as a single HLS IP core. This project was implemented by our Xilinx partner, thus I have little experience with it. But you can give it a try.

I am not sure if it helps. If you still are having problems, please supply the Vivado version and the project you are trying to open.

If you have further questions, don't hesitate to ask.


Best regards,
Andrei
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